- SpaceX (Bastrop, TX)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- SpaceX (Sunnyvale, CA)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- Meta (Sunnyvale, CA)
- … Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC . Analyze the inter-block timing and come up with IO budgets for ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...Timing /physical libraries, SRAM Memories 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with… more
- Meta (Sunnyvale, CA)
- …tools 10. Experience with Lint, Clock Domain & Reset Domain crossing 11. Experience with SOC CDC signoff 12. Knowledge of SOC Integration (Clocking, Reset, ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static… more
- Amazon (Sunnyvale, CA)
- …advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. * Work for Systems and Architecture, SoC ... STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development,...and Signoff for a complex, multi-clock, multi-voltage SoC . * Streamlining the timing signoff… more
- Meta (Sunnyvale, CA)
- …designs, responsible for floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, DFT, ... from transistor, through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you...joining Meta 6. 3+ years of hands-on experience in ASIC physical design with solid understanding of digital design… more
- Broadcom (San Jose, CA)
- …for backend development, floorplan, guidelines for Place and Route.** + **Evaluating timing signoff , verification and IP Integration and system level ... performance, power, and cost over the project lifetime.** + **Experience in driving SOC level front end design specifications and other documentation in a clear and… more
- Cisco (San Jose, CA)
- …bump and rdl planning, power grid design to clock planning, routing, and timing closure. + Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, ... provide solutions and ensure signoff clean results. + Work closely with block and...Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification + Experience in deep… more