- Broadcom (Fort Collins, CO)
- …by delivering best in class technology platforms, easy to integrate bleeding edge intellectual property , and by providing world class customer support. APD's ... wireless solutions, as some examples. The _Interface and Analog IP RTL Design Manager_ position is part...design techniques and tools + Experience with HBM, DDR , die-to-die PHY development + Program Management skills -… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr . Physical Design Engineer to continue to innovate on behalf of our customers. ... analysis, physical verification, and ECO - 7+ years integrating IP and ability to specify and drive IP...design challenges across various technologies such as CPU, DDR , PCIe, fabrics etc. - Experience in extraction of… more
- Amazon (Cupertino, CA)
- …closure, IR drop analysis, physical verification, ECO and sign-off - Develop physical design methodologies - Evaluate 3rd party IP and provide recommendations - ... of device physics, custom/semi-custom implementation techniques - Experience solving physical design challenges across various technologies such as DDR , PCIe,… more
- Amazon (Austin, TX)
- …raise the bar in implementing state-of-the-art machine learning hardware. Key job responsibilities - Design and implement custom cells / IP . - Develop & run ... organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS,… more
- Amazon (Cupertino, CA)
- …ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design , bring up, Characterization and validation. A day in ... generation ML Chips, Cards and server integration. As a senior member of our platform development team, you will...training, timing parameters and/or controller features - Drive the IP Integration and design of silicon and… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... and supporting our prototyping methodology. + **Option to engage in block-level RTL design or block or top-level IP integration.** + Collaborate with Software,… more
- Qualcomm (San Diego, CA)
- …SERDES Interfaces such as PCIe, USB4, UFS, DP, MIPI(DSI,CSI), PLLs and leading edge LP- DDR & PC- DDR Subsystem components (DRAM, DRAM Controller, Mixed Signal PHY ... IP , IOs, Clocking architecture, Delay circuits, Power Distribution Network)...executing characterization plans for High Speed Interfaces to optimize design parameters and validate electrical compliance, driving corresponding first… more
- Amazon (Cupertino, CA)
- …ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design , bring up, Characterization and validation. A day in ... knowledge of DDR /HBM training, timing parameters and/or controller features -Drive the IP Integration and design of silicon and 2.5D packaging -Support the… more
- Microsoft Corporation (Santa Clara, CA)
- …experience. + 5+ years of experience of DDR4~5 or LPDDR5 Protocols, Cache design or Inter-Cluster Cache Coherency, like MESI protocol . **Other Requirements:** + ... Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer. You will join our front-end silicon...**Preferred Qualifications:** + Hands-on experience in integrating 3rd party IP , such as DDR Controller/PHY and PLLs.… more
- Capgemini (Minneapolis, MN)
- …of analog/mixed-signal IP (eg, SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.) * Experience leading complex layout macros during ... **About the job you're considering** * 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent… more
- Microsoft Corporation (Raleigh, NC)
- …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Silicon Firmware Engineer** to join our silicon libraries firmware team covering ... silicon firmware code focusing on mesh interconnects, in partnership with architecture, design , design verification, and software teams. + Work in pre-silicon… more
- Qualcomm (San Diego, CA)
- …connected future for all. As a Qualcomm GPU Engineer, you may architect, design , implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm ... all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis &...of the synthesized FPGA RTL. + Work on third-party IP integration and system-level debugging. + System level RTL… more
- Micron Technology, Inc. (Boise, ID)
- …overall product yields and equipment efficiency to maximize ROI. + Work closely with design teams to develop design for test features to drive lower costs ... development. + Solid understanding of testing for CMOS SoCs. DDR , and ONFI. (this is standard testing terminology) +...MXS test programming and debug experience. Familiar with testing IP blocks such as PLL, efuse, LDOs, PCIe, +… more