- Northrop Grumman (Morrisville, NC)
- …work of your career. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, ... maintain an active DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for static timing analysis on digital designs to ensure timing … more
- Google (Sunnyvale, CA)
- …or a related field, or equivalent practical experience. + 2 years of experience in static timing analysis . + Experience in Primetime or Tempus Tcl scripting ... and static timing analysis debug and problem solving. + Experience in sub chip timing sign-off checklist criteria and overseeing final timing … more
- Meta (Sunnyvale, CA)
- …Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- Meta (Sunnyvale, CA)
- … timing analysis , SI noise analysis 11. Experience with running Static Timing Analysis for full chip using DMSA 12. Knowledge of front-end and ... experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip… more
- NVIDIA (Santa Clara, CA)
- …years experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …+ 8+ years experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...+ You will be responsible for all aspects of timing including, timing analysis and… more
- NVIDIA (Westford, MA)
- … tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon...be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints...development in functional and test modes + Experience in Static Timing Analysis and prior ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. + Experience in Static Timing Analysis and prior working experience with STA tools ... ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US +… more
- NVIDIA (Austin, TX)
- …Engineering or Device Physics (or equivalent experience) + 8+ years experience in gate-level static timing analysis and/or power analysis + Proficiency ... algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale...algorithms for large scale and high accuracy gate-level power, timing , parasitic, and noise analysis . A deep… more
- SanDisk (Milpitas, CA)
- …entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis , logic equivalence, DFT insertion, place-and-route, ... of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory...clock tree synthesis, extraction, static timing analysis , physical verification)… more
- Cadence Design Systems, Inc. (Austin, TX)
- …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... seminars within Cadence and customer sites. Requirements; 10+ years of experience in Static timing analysis , Individual should be able to lead and execute… more
- Northrop Grumman (Annapolis Junction, MD)
- …to obtain and maintain a TS/SCI clearance.** **Preferred Qualifications:** **Strong background in static timing analysis and timing characterization ... to obtain and maintain a TS/SCI clearance.** **Preferred Qualifications:** **Strong background in static timing analysis and timing characterization… more
- Broadcom (Fort Collins, CO)
- …- Deep understanding of PLLs and clock networks Significant experience using a static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence ... Crosstalk Delay, and Glitch/Noise Analysis - Understanding of setup analysis , hold analysis , and other timing checks - Ability to understand and… more
- Micron Technology, Inc. (Richardson, TX)
- …expertise in design optimization for performance and low power consumption, including UPF, static timing analysis , synthesis design constraints, and closing ... the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design and develop next-generation HBM DRAM products. You… more
- Teradyne (North Reading, MA)
- …Understanding in the areas of electromagnetic field and transmission line theory, reflection and static timing analysis , PCB and Package design for power ... models for full Board level Signal and Power Integrity Analysis . Use of 2D and 3D quasi- static ,...simulation of PCB's & packages for signal/power integrity and timing analysis . + Familiarity with IBIS models… more
- Micron Technology, Inc. (Richardson, TX)
- …test code in System Verilog. + Experience dealing with clock domain crossings (CDC), static timing analysis , synthesis design constraints, and closing ... advance faster than ever. As an HBM SOC Design Engineer , you will be responsible for the design &...developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static… more