• Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...The team is also handling the architecture, design, and synthesis of multiple System-level modules. What you'll be doing:… more
    NVIDIA (09/17/25)
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  • ASIC Implementation Engineer

    Meta (Austin, TX)
    Implementation Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification ... Design for Testability coverage for Stuck-at faults 5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist… more
    Meta (09/23/25)
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  • ASIC Engineer

    Meta (Sunnyvale, CA)
    …this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL- synthesis and PrimeTime-STA for blocks and top-level including SOC. 11. Analyze… more
    Meta (09/20/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
    SpaceX (09/11/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Bastrop, TX)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
    SpaceX (09/11/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...timing constraint for those IPs and support the physical implementation team ( synthesis , timing closure, formality check)… more
    SpaceX (08/22/25)
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  • Senior FPGA/ ASIC Engineer (Onsite)

    RTX Corporation (Cedar Rapids, IA)
    …or Computer Engineer that will be involved in the design, implementation , verification and integration of a wide variety of high-performance ASICs, FPGAs, and ... you interested in becoming part of a growing Avionics FPGA/ ASIC team? This position is for a highly experienced,...SoPCs for Collins Avionics solutions. As an engineer in this organization, you will be employing best… more
    RTX Corporation (08/01/25)
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  • ASIC /SOC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...within Subsystems + Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum… more
    SpaceX (09/18/25)
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  • Senior Electrical Engineer - ASIC

    RTX Corporation (Cedar Rapids, IA)
    …for a security clearance **Security Clearance:** DoD Clearance: Secret **Senior Electrical Engineer ** **- ASIC /FPGA (Onsite)** This position is for a motivated ... Computer engineering candidate to be involved in the design, implementation , verification, and integration of a wide variety of...blocks using VHDL or System Verilog. + Proficiency using ASIC and/or FPGA simulation and synthesis tools… more
    RTX Corporation (07/25/25)
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  • ASIC Engineer , Physical Design

    Meta (Austin, TX)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
    Meta (08/29/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis , static timing analysis. You will either be responsible for block and/or chip level design and… more
    Broadcom (07/26/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... of ASIC design flow including RTL design, verification, logic synthesis , timing analysis, ECO, and post silicon debug. + Strong interpersonal skills… more
    NVIDIA (07/31/25)
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  • ASIC /FPGA Design Engineer (Compute…

    Teradyne (North Reading, MA)
    …better business results. Opportunity Overview Our Hardware Engineering team is seeking an FPGA/ ASIC Design Engineer to work with a multi-disciplined team to ... Creation of physical design constraints for placement, timing closure and CDC + Implementation of designs into target technologies using synthesis and place and… more
    Teradyne (08/26/25)
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  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis , equivalence checking, floor-planning, timing constraints, timing… more
    NVIDIA (08/23/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …power, and area targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis , equivalence checking, floor-planning, ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
    NVIDIA (08/13/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation ,...+ Experience in RTL design (Verilog), verification and logic synthesis . + Strong coding skills in python or other… more
    NVIDIA (07/29/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...test plan development and debug 6. Collaboration with the implementation team to close the design on timing and… more
    Meta (08/01/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 4. Collaboration with implementation team to close the design on timing and… more
    Meta (08/01/25)
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  • ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis , equivalence checking, floor-planning, timing constraints, timing… more
    NVIDIA (09/20/25)
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  • ASIC Design Engineer - Hardware

    NVIDIA (Austin, TX)
    …make a lasting impact on the world. Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving ... + Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/ implementation flow, and design automation + Good understanding of SOC… more
    NVIDIA (09/17/25)
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