- Advanced Micro Devices, Inc (Santa Clara, CA)
- …of high-speed Server DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity ... and ready to take on problems. KEY RESPONSIBILITIES: Microarchitectural design and RTL implementation of IP features. PHY...team to develop firmware sequences and algorithms Analyze RTL design for power optimization and timing optimization… more
- General Motors (Warren, MI)
- …such as SoCs, MCUs, PCIe, DDR , UFS, eMMC, GMSL, FPD-Link, Ethernet Switches, PHY , CAN, power supply design , etc. Strong proficiency in circuit design , ... and development of a Compute hardware platform (from concept design to launch) while meeting cost, timing ,...concept design to launch) while meeting cost, timing , quality, and safety targets Collaborate with cross-functional teams,… more
- Microsoft Corporation (Hillsboro, OR)
- … DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual ... Property (IP) and/or Double Data Rate ( DDR ) subsystem integration with Physical Layer ( PHY ) + Learn about the design and interact with partner teams to… more
- Amazon (Cupertino, CA)
- … DDR /HBM at the PHY and controller level -Good knowledge of DDR /HBM training, timing parameters and/or controller features -Drive the IP Integration and ... customers change the world. We are seeking an HBM/DDRx Phy expert with role in the definition, design... of silicon and 2.5D packaging -Support the physical design team, review clocking and timing constraints… more
- Amazon (Cupertino, CA)
- … DDR /HBM at the PHY and controller level - Good knowledge of DDR /HBM training, timing parameters and/or controller features - Drive the IP Integration and ... customers change the world. We are seeking an HBM/DDRx Phy expert with role in the definition, design...of silicon and 2.5D packaging - Support the physical design team, review clocking and timing constraints… more
- Qualcomm (Santa Clara, CA)
- …driving JEDEC or similar standardization is a plus **Preferred Qualifications:** + Experience in DDR design specifications such as DDR and LPDDR + Experience ... **Minimum Qualifications:** + 8+ years of experience with 5+ years in DDR /SerDes in Package/PCB/System Design related to compute/server standards. + Experience… more
- General Motors (Warren, MI)
- …such as SoCs, MCUs, PCIe, DDR , UFS, eMMC, GMSL, FPD-Link, Ethernet Switches, PHY , CAN, power supply design , etc. + Strong proficiency in circuit design ... and development of a Compute hardware platform (from concept design to launch) while meeting cost, timing ,...concept design to launch) while meeting cost, timing , quality, and safety targets + Collaborate with cross-functional… more
- General Motors (Warren, MI)
- …such as SoCs, MCUs, PCIe, DDR , UFS, eMMC, GMSL, FPD-Link, Ethernet Switches, PHY , CAN, power supply design , etc. + Strong proficiency in circuit design ... through to mass production, while maintaining quality, cost, and timing targets + Lead electrical schematic design ...and timing targets + Lead electrical schematic design and PCB layout in Mentor Graphics + Ownership… more
- Micron Technology, Inc. (Folsom, CA)
- …of high speed I/O design + Hands on experience in High-Speed IO PHY architecture definition + Proven understanding of industry HSIO protocols like DDR , PCIe, ... years of experience in memory address and data path architecture/ design + 5+ years of experience in system ...design + 5+ years of experience in system timing budgeting + Deep understanding of signal integrity, channel… more
- Microsoft Corporation (Santa Clara, CA)
- …plans and methodology. + Collaborate with Physical design teams to ensure design meets timing and area requirements. + Work on post-silicon verification and ... + Own the micro-architecture specification and RTL development of design modules for ASIC memory subsystem. + Review and...Hands-on experience in integrating 3rd party IP, such as DDR Controller/ PHY and PLLs. + Proven experience… more
