• ASIC Implementation Engineer

    Meta (Austin, TX)
    … Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform ... technical field, or equivalent practical experience 9. 6+ years of experience in static verification tools 10. Experience with Lint, Clock Domain & Reset Domain… more
    Meta (09/23/25)
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  • ASIC and/or FPGA Design & Verification…

    The Boeing Company (Tukwila, WA)
    …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... of ASIC /FPGA design or verification experience + Experience with ASIC /FPGA architectural definition, and detailed design implementation and functional… more
    The Boeing Company (09/17/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC more
    SpaceX (09/11/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Bastrop, TX)
    …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC more
    SpaceX (09/11/25)
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  • ASIC Engineer

    Meta (Sunnyvale, CA)
    …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis ... Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 Static timing analysis and verification at different PVT corner 20. 5. Timing ECO… more
    Meta (09/20/25)
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  • Senior FPGA/ ASIC Engineer (Onsite)

    RTX Corporation (Cedar Rapids, IA)
    …or Computer Engineer that will be involved in the design, implementation , verification and integration of a wide variety of high-performance ASICs, FPGAs, and ... you interested in becoming part of a growing Avionics FPGA/ ASIC team? This position is for a highly experienced,...SoPCs for Collins Avionics solutions. As an engineer in this organization, you will be employing best… more
    RTX Corporation (08/01/25)
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  • ASIC Engineer , Physical Design

    Meta (Austin, TX)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
    Meta (08/29/25)
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  • ASIC /FPGA Design Engineer (Compute…

    Teradyne (North Reading, MA)
    …better business results. Opportunity Overview Our Hardware Engineering team is seeking an FPGA/ ASIC Design Engineer to work with a multi-disciplined team to ... design constraints for placement, timing closure and CDC + Implementation of designs into target technologies using synthesis and...place and route tools + Perform timing analysis using static timing analysis tools. + Perform lab debug of… more
    Teradyne (08/26/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
    Broadcom (07/26/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... area targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking,...path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.… more
    NVIDIA (08/13/25)
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  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
    NVIDIA (08/23/25)
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  • ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
    NVIDIA (09/20/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation . What we need to see: + Hold a BS in Electrical or… more
    NVIDIA (09/09/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
    NVIDIA (09/10/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
    NVIDIA (09/23/25)
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  • Sr. CAD Engineer , ASIC

    Amazon (San Diego, CA)
    …high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA tools and flows ... of the design automation and methodology team and deliver digital design implementation flows to design teams using various silicon processes - Develop, regress,… more
    Amazon (09/05/25)
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  • Electrical Engineer Intern - FPGA Design…

    L3Harris (Camden, NJ)
    …land, sea and cyber domains in the interest of national security. Job Title: ASIC /FPGA VHDL Design Engineer (Entry Level) Job Code: EEIC Job Location: Camden, ... NJ Schedule: 9/80 Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the intern Member of Engineering Staff (AMES) will be part of the key design… more
    L3Harris (09/05/25)
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  • Principal Digital Engineer

    Renesas (Austin, TX)
    …coding and ASIC design methodology** + Expertise in digital design implementation , including logical synthesis and DFT insertion with high coverage + Experience ... Principal Digital Engineer Job Description Renesas is seeking a talented...verification reviews + Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking + Create… more
    Renesas (09/23/25)
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  • Design Engineer Architect/Lead

    Broadcom (Fort Collins, CO)
    …the physical design team to aid in overall closure and manufacture of the ASIC with emphasis on low power, optimized area, max. performance and high overall ... candidate should have a strong understanding of VLSI and ASIC physical design 12+ years of experience w/ a...of PLLs and clock networks Significant experience using a static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence… more
    Broadcom (09/10/25)
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  • Senior Security Firmware Engineer

    SanDisk (Irvine, CA)
    …the Firmware on SoC platforms, as well as bringing up of FPGA and ASIC . + Contribute to the Security Development Lifecycle of the Firmware by supporting its ... development at different stages, including design, threat analysis, implementation , validation, vulnerability testing, certification, and audit. **Qualifications** **REQUIRED:**… more
    SanDisk (09/18/25)
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