- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, ... provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco...and guide them in refining design and timing constraints for seamless physical design… more
- Northrop Grumman (Linthicum Heights, MD)
- …+ Work closely with design , verification, design -for-test and physical design teams to optimize the timing and improve design performance + ... maintain timing methodologies and flows for efficient timing analysis and closure + Conduct design ...+ Experience in the full product life cycle of ASIC Design + Effective communication and presentation… more
- NVIDIA (Santa Clara, CA)
- …Electrical or Computer Engineering or equivalent experience. + 8+ years experience in Physical design / Timing . + Experience in full-chip/sub-chip Static ... generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- NVIDIA (Santa Clara, CA)
- …with 5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO ... and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd:… more
- Cisco (Maynard, MA)
- Senior ASIC Timing Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1449290) + Location:Maynard, Massachusetts, US + Area of InterestEngineer - ... Work closely with RTL designers to debug and root-cause timing issues related to design , tools, etc....power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- NVIDIA (Westford, MA)
- …to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- The Boeing Company (Huntington Beach, CA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities:...cross-functional teams, IP, and EDA vendors 11. Experience in physical design and timing closure… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality… more
- NVIDIA (Santa Clara, CA)
- …and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design ... What you will be doing: + Working with architects, design leads, physical design leads...Drive the area review process and collaborate with the ASIC design team to identify area, interconnect… more
- Teradyne (North Reading, MA)
- …interface protocols + Use of digital simulation tools to verify designs. + Creation of physical design constraints for placement, timing closure and CDC + ... Opportunity Overview Our Hardware Engineering team is seeking an FPGA/ ASIC Design Engineer to work with a...such as Python, TCL and Perl + Experience with physical design tools from FPGA vendors (Vivado… more
- Google (Sunnyvale, CA)
- …+ Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design . **About the job** In this ... Technical Lead Manager, ASIC Design , Machine Learning _corporate_fare_ Google...power and area design goals, and explore RTL/ design trade-offs for physical design … more
- NVIDIA (Santa Clara, CA)
- …. + A deep understanding of ASIC design flow including RTL design , verification, logic synthesis, timing analysis, ECO, and post silicon debug. + Strong ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design...verification engineers. + Deliver a synthesis/ timing clean design while working with the physical … more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design . You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis....have strong UNIX-based EDA tool skills and knowledge of ASIC design flows. Must be familiar with… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of...functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more