- Cadence Design Systems, Inc. (San Jose, CA)
- …challenging custom IC and system design and simulation problems using Cadence technology. This is a customer-facing application engineering (AE) role where you ... At Cadence , we hire and develop leaders and innovators...verbal communication skills. Responsibilities include: + Understanding customers' custom IC design, simulation and layout challenges +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …the development of product roadmaps and positioning in the market place of the Cadence IC Packaging, SiP and Co-Design solution. This person will be responsible ... published and/or presented material, and a passion to increase Cadence IC Packaging market share by developing...design including, but not limited to, systemlevel design, ICP layout , integration with corporate systems for partand design life… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …environment + Position requires proficiency in using CAD tools for circuit simulation, layout , and physical verification + Cadence tool experience, lab test ... At Cadence , we hire and develop leaders and innovators...impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development… more
- MIT Lincoln Laboratory (Lexington, MA)
- …integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg, silicon, compound-semiconductor, ... of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and heterogeneous/hybrid… more
- Medtronic (Mounds View, MN)
- … layout directions that drive signal integrity, matching, thermal, etc. * Direct and review IC layout activities within Cadence Layout tools. * Create ... the Medtronic CRHF Device Development organization will have responsibility for IC design, circuit requirements definition, simulation analysis, layout … more
- Teledyne (Camarillo, CA)
- …background with CMOS semiconductor IC design including performing full custom analog IC layout . + Thorough understanding of deep sub-micron layout design ... Sensors is looking for a **Senior Analog Mixed Signal IC Design engineer** responsible for supporting the Read Out...Strong background with full custom circuit, block, and chip layout using Cadence Virtuoso tools, Layout… more
- Micron Technology, Inc. (Boise, ID)
- …other countries and leverage vast resources available throughout Micron sites.** **Provide layout supervision, as well as optimize layout throughout post- ... simulations.** **Qualifications** **Demonstrated experience in mix-signal, digital, or analog IC design and development for volatile or nonvolatile memory… more
- Power Integrations (San Jose, CA)
- …and maintains PDKs. + Supports all IC design CAD tools such as Cadence schematic entry, mixed mode circuit simulation, layout design, layout ... management, user support and vendor interface. + Works with IC layout designers providing support for taping...languages + Experience with Encounter P&R + Experience with Cadence VSR & EMIR + Understanding Semiconductor Process Flow… more
- BAE Systems (Nashua, NH)
- …your career with BAE Systems. BAE Systems Engineering is looking for an IC CAD/EDA tools engineer to help support our Mixed-Signal Integrated Circuit design team ... The candidate should also have considerable expertise in the Linux environment, IC CAD tools, PDKs, and semiconductor foundry capability. Responsibilities include: +… more
- Skyworks (Cedar Rapids, IA)
- …a schedule, and have strong teamwork skills Preferred Skills * Experience using Cadence Virtuoso analog IC design tools for analog/mixed-signal design and ... Sr. Analog IC Design Engineer Apply now " Date:May 25,...product definition, architecture, system, transistor-level circuit design, MCM design, layout / layout supervision, lab debug and production support.… more
- Cisco (San Jose, CA)
- …with IC Package or PCB development * Fluent in Cadence Allegro Package Designer * Strong communication and documentation skills Preferred Qualifications: ... are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D… more
- Cadence Design Systems, Inc. (San Jose, CA)
- At Cadence , we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for an engagement focused Product ... (PE) in the Digital and Signoff Group (DSG) at Cadence . The Cadence DSG will offer you...highly competent PE team with extensive PPA tuning and Layout experience, having experience of either RTL design and/or… more
- Broadcom (San Jose, CA)
- …circuits in deep submicron process -Solid knowledge of precision and low noise analog layout techniques -High proficiency in driving Cadence Virtuoso XL GXL ... Account, please Sign-In before you apply.** **Job Description:** + Layout design of high precision analog / mixed signal...7nm FinFet -Knowledge of I/O, ESD, packaging, CAD setup, Cadence SKILL and Unix scripting is a plus -A… more
- Broadcom (San Jose, CA)
- …interposers. Experience with interposer designs including CoWoS, 2.5D/3D integration using Cadence Innovus/Integrity or Synopsys 3DIC compiler is a must. Candidates ... design, including CoWoS, 2.5D/3D + Proficiency with EDA tools such as Cadence (Innovus, Integrity), Synopsys (3DIC compiler), Mentor Graphics (Calibre) for layout… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Hands-on experience in physical verification flows and/or runset development for Custom IC / Digital platform or layout experience. + Strong problem-solving, ... At Cadence , we hire and develop leaders and innovators...Supporting technical evaluations/benchmarks and driving the process to deliver Cadence solutions. + Developing an understanding of the customer's… more
- Qualcomm (Santa Clara, CA)
- …or professional experience using two or more of the following software: CADENCE , Virtuoso, ADS. **Preferred Qualifications:** * 3+ years experience in the transistor ... circuits perform under various circumstances. * Lead others to floor-plan layout ; collaborates with layout engineers to generate the layout of circuits and… more
- Northrop Grumman (Baltimore, MD)
- …and filters. + Familiarity with schematic entry and simulation tools such as Cadence ADE, Explorer/Assembler, Virtuoso, and Spectre. + Experience with the use of the ... margin, PSRR over process/voltage/temperature corners. + Proficiency with integrated circuit layout and best practices to ensure good component matching and minimize… more
- Capgemini (San Jose, CA)
- …converters, digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ... industry. **Key responsibilities:** + .We will be designing analog layout using industry standard EDA tools from Cadence...layout in advanced CMOS process. + .Experience in IC layout of cutting-edge high-performance, high-speed CMOS… more
- Capgemini (Santa Clara, CA)
- …**Your skills and experience** + Proficient in developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies ... + 7 years of experience in analog and RF layout design, including leadership of IC layouts...thermal and electro migration-aware techniques. + Proficient in Synopsys, Cadence , and Mentor layout tools; Python scripting… more
- Broadcom (San Jose, CA)
- …and Analog RF IC Physical Design. + Experience developing and leading complex layout IC for high speed applications in advanced CMOS FinFET technologies such ... years of experience in Mixed Signal and Analog RF IC Physical Design or MS in Electrical Engineering, Computer...+ Thorough knowledge of industry standard EDA tools from Cadence , Mentor and Synopsys. + Experience with layout… more