- Capgemini (San Jose, CA)
- …digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated ... **Required Skills** + .10 years' experience in high performance analog layout in advanced CMOS process. + .Experience in IC layout of cutting-edge… more
- NVIDIA (Santa Clara, CA)
- …5 years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout , and VLSI design. + Experience working with standard cell ... design & layout . + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a… more
- NVIDIA (Santa Clara, CA)
- …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL, C++, tcl. + Great interpersonal skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our… more
- NVIDIA (Santa Clara, CA)
- …of Photonics, CMOS , Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ... design experience + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. Validated...of analog circuit layout concepts in submicron CMOS technologies. Validated experience with Cadence custom circuit design… more
- Micron Technology, Inc. (Boise, ID)
- …the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer, you will play a crucial role in the ... development of current and future CMOS technology. You will be responsible for device and...with teams across the organization including Process, Circuit, Design, Layout , Product Engineering, and Modeling/TCAD. Your expertise will be… more
- NVIDIA (Santa Clara, CA)
- …integration would be excellent to have. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies + Validated experience with Cadence ... If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to...circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools + You'll work with… more
- Skyworks (Hillsboro, OR)
- …Amplifiers, PMU and Switching regulators + Advanced knowledge of device physics, CMOS fabrication processes, layout tradeoffs for high performance circuits + ... Hands on experience with SOC debug, validation, characterization, test techniques and equipment + Strong knowledge of IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. + Ability to work in a dynamic environment with changing needs and… more
- NVIDIA (Santa Clara, CA)
- …LVS decks such as Dracula, Hercules, Calibre. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + Experience with analog ... from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join...blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools. + You'll work multi-functional… more
- Power Integrations (San Jose, CA)
- …is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. + Verbal and reading, ... skills in Mandarin is required. + Excellent English speaking, reading and technical writing skill is required. + Candidates with direct experience in customer interface on resolution of customer quality problems will be given special consideration. +… more
- Power Integrations (San Jose, CA)
- …+ Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Preferences will be given ... to candidates who have a thorough understanding of analog, mixed-signal, or power semiconductor operational characteristics and the ability to apply fault isolation techniques at chip level as well as PCB at power supply system level. Education: + Must have BS… more
- MIT Lincoln Laboratory (Lexington, MA)
- …(CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting ... vertically integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg, silicon, compound-semiconductor,… more
- NVIDIA (Santa Clara, CA)
- …Photonics, CMOS , Electronics, and Systems engineers + Conduct chip layout circuit design, circuit checking, and device evaluation and characterization. + ... design experience + Deep understanding of analog circuit layout and Silicon Photonic concepts in CMOS ...circuit layout and Silicon Photonic concepts in CMOS and SiPhtechnologies. Validated experience with Cadence custom circuit… more
- Broadcom (San Jose, CA)
- …developing and leading complex layout IC for high speed applications in advanced CMOS FinFET technologies such as 5nm and 3nm at the block level and chip level. ... for an experienced RFIC and Analog Mixed-Signal Physical Design and Layout Engineer **Qualifications include:** + BS in Electrical Engineering, Computer Engineering… more
- NVIDIA (Santa Clara, CA)
- …experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + You are an authority with ... hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a...to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. + You'll work cross… more
- NVIDIA (Santa Clara, CA)
- …experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + You are an authority with ... This is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking… more
- Qualcomm (San Diego, CA)
- …experience + Hands on Scan/ATPG/MBIST debug + Sound theoretical knowledge of Digital/Analog CMOS circuits + Experience with CAD layout tools Hands on experience ... semiconductor IC Failure Analysis experience in: + Structural debug (ATPG) for yield + Fault isolation techniques: Emission Microscopy, LASER based stimulation techniques; LIVA/TIVA/CTM, Thermal emission, Curve tracer, X-ray imaging etc., + Tools/techniques… more
- Micron Technology, Inc. (Boise, ID)
- …faster than ever. You will be part of the development of next generation CMOS devices employed in the most ground breaking Memory and Compute in Memory products. ... Responsible for developing devices or modules involved in novel CMOS solutions for the future generations of DRAM and emerging memories necessary to meet the… more
- MIT Lincoln Laboratory (Lexington, MA)
- …(CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting ... vertically integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg, silicon, compound-semiconductor,… more
- NVIDIA (Santa Clara, CA)
- …is a plus + Prior experience in designing switched power/ RF circuits on CMOS and demonstrating good understanding of layout considerations for reliability and ... ageing is a plus + Prior leadership experience is a plus. NVIDIA is a pioneer in bringing groundbreaking technology to new markets. We have some of the most forward-thinking and hardworking people in the world working with us. If you're creative and… more
- Sandia National Laboratories (Albuquerque, NM)
- …of a broad understanding of a variety of microsystems technologies ( CMOS , MEMS, photonics, III-V semiconductors, etc.) and heterogeneous integration technologies to ... relevant STEM field + Experience with integrated circuit design, simulation/verification, and layout , particularly in Cadence tools + Ability to acquire and maintain… more