- Raytheon (Mckinney, TX)
- …such as HPAs, LNAs, PSAs, TDUs, or High power switches in GaN, GaAs, or CMOS . The candidate will be responsible for the complete development cycle of the MMIC, ... including selection of the technology node, RF and DC topology, layout , test, evaluation, and interfacing with the internal customer. The work is focused on Gallium… more
- Capgemini (San Jose, CA)
- …digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated ... **Required Skills** + .10 years' experience in high performance analog layout in advanced CMOS process. + .Experience in IC layout of cutting-edge… more
- NVIDIA (Santa Clara, CA)
- …5 years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout , and VLSI design. + Experience working with standard cell ... design & layout . + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a… more
- Teradyne (Agoura Hills, CA)
- …ATE (Automatic Test Equipment) instruments. We are looking for a candidate with CMOS design and layout experience who has successfully taped-out several designs. ... that satisfy required performance + Provide guidance for physical implementation ( layout ) of high-speed circuits + Optimization of circuits via simulation (with… more
- NVIDIA (Santa Clara, CA)
- …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL, C++, tcl. + Great interpersonal skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our… more
- NVIDIA (Santa Clara, CA)
- …Engineering and 4+ year's experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design + Excellent programming skills + Experience ... with perl, Cadence SKILL, python, tcl + Great communication skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth,… more
- NVIDIA (Santa Clara, CA)
- …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Understanding of version control software ... preferably Perforce. + Understanding the regression testing methodology. + Excellent programming skills; experience with perl, python and other scripting languages. + Great interpersonal skills + Passionate about providing excellent support for end-users.… more
- NVIDIA (Santa Clara, CA)
- …5+ years of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL. + Expertise in ICV in order to support, enhance, and debug foundry DRC and LVS techfiles. + Being able to implement NVIDIA specific DFM, DRC rules using ICV. + Add NVIDIA specific devices in the LVS deck using ICV. + Great interpersonal… more
- Micron Technology, Inc. (Boise, ID)
- …the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer, you will play a crucial role in the ... development of current and future CMOS technology. You will be responsible for device and...with teams across the organization including Process, Circuit, Design, Layout , Product Engineering, and Modeling/TCAD. Your expertise will be… more
- NVIDIA (Santa Clara, CA)
- …integration would be excellent to have. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies + Validated experience with Cadence ... If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to...circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools + You'll work with… more
- Skyworks (Andover, MA)
- …Amplifiers, PMU and Switching regulators + Advanced knowledge of device physics, CMOS fabrication processes, layout tradeoffs for high performance circuits + ... Hands on experience with SOC debug, validation, characterization, test techniques and equipment + Strong knowledge of IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. + Ability to work in a dynamic environment with changing needs and… more
- Power Integrations (San Jose, CA)
- …is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. + Verbal and reading, ... skills in Mandarin is required. + Excellent English speaking, reading and technical writing skill is required. + Candidates with direct experience in customer interface on resolution of customer quality problems will be given special consideration. +… more
- Power Integrations (San Jose, CA)
- …+ Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Preferences will be given ... to candidates who have a thorough understanding of analog, mixed-signal, or power semiconductor operational characteristics and the ability to apply fault isolation techniques at chip level as well as PCB at power supply system level. Education: + Must have BS… more
- MIT Lincoln Laboratory (Lexington, MA)
- …(CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting ... vertically integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg, silicon, compound-semiconductor,… more
- Capgemini (Santa Clara, CA)
- …a Senior Analog Layout Design Engineer with deep expertise in advanced CMOS FinFET technologies (TSMC 7nm, 5nm, 3nm). The ideal candidate will collaborate with ... and experience** + Proficient in developing and leading complex layout IC for high-speed applications in advanced CMOS... layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and 3nm at… more
- NVIDIA (Santa Clara, CA)
- …Photonics, CMOS , Electronics, and Systems engineers + Conduct chip layout circuit design, circuit checking, and device evaluation and characterization. + ... design experience + Deep understanding of analog circuit layout and Silicon Photonic concepts in CMOS ...circuit layout and Silicon Photonic concepts in CMOS and SiPhtechnologies. Validated experience with Cadence custom circuit… more
- Broadcom (San Jose, CA)
- …developing and leading complex layout IC for high speed applications in advanced CMOS FinFET technologies such as 5nm and 3nm at the block level and chip level. ... for an experienced RFIC and Analog Mixed-Signal Physical Design and Layout Engineer **Qualifications include:** + BS in Electrical Engineering, Computer Engineering… more
- NVIDIA (Santa Clara, CA)
- …experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + You are an authority with ... hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a...to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. + You'll work cross… more
- Qualcomm (San Diego, CA)
- …expertise and knowledge. **Preferred Qualifications:** + Sound theoretical knowledge of Digital/Analog CMOS circuits. + Experience with CAD layout tools. Ability ... to analyze layout and convert to basic schematics. + Understanding of circuit function and relation to failure signatures. + Excellent data analysis and problem-solving skills. + Strong interpersonal skills and ability to work effectively within a… more
- NVIDIA (Austin, TX)
- …industry experience in Mask and Layout Design. + Deep understanding of layout concepts in submicron CMOS technologies. + Expertise with Cadence custom ... hear from you! We are seeking a Senior Mask Layout Design Engineer to join our growing and dynamic...capacitors used in all NVIDIA products, utilizing state-of-the-art sub-micron CMOS technologies and Cadence tools. + Collaborate with a… more
