- Microsoft Corporation (Mountain View, CA)
- …and optimize the Cloud infrastructure. We are looking for a **Principal Physical Design Engineer ** with ** CPU Core expertise** to join the team. \#SCHIE #CSME ... \#Siliconjobs #CCDO **Responsibilities** + Responsible for Core CPU partition (L1-L2) or similar ownership with PPAS (Power, Performance, Area & Schedule) target… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT ), Place & Route and Static Timing Analysis (STA).You may get involved… more
- NVIDIA (Santa Clara, CA)
- …Clocking. + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in ... The clocks group is looking for an outstanding ASIC engineer to join the team. The Team is responsible...is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the design ... of CPU on-chip interconnect network and last-level caches , working...design flow including RTL design, verification, logic synthesis, prototyping, DFT , timing analysis, floor-planning, ECO, bring-up & lab debug.… more
- NVIDIA (Santa Clara, CA)
- …Clocking. + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in ... The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design… more
- Microsoft Corporation (Mountain View, CA)
- …and augmented reality. We are looking for a ** ** **Principal Analog Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) ... Interface with architecture, physical design (PD), design for test ( DFT ), and other teams to optimize tradeoffs within the...QA and Release process, Integration of IPs in major CPU , GPU or AI accelerator SoC's and close interactions… more
- NVIDIA (Santa Clara, CA)
- …drive innovation. We are now looking for a Senior Product Development Engineer to join our outstanding DataCenter/Automotive/Embedded Chips team! We specialize in ... microelectronics. We are seeking a highly skilled and motivated Product Development engineer to drive bring up of state-of-the-art SOCs through collaboration with… more
- Mercury Systems (Cypress, CA)
- …the most rugged environments. We have a career opportunity for an electrical engineer to provide technical oversight and direction to the hardware design team. This ... (DFM), design for assembly (DFA) and design for test ( DFT ) + Provide technical leadership for new and on-going...on proposals and schedule/cost estimates + Experience with Intel CPU design + Working knowledge of VITA design standards… more
- Honeywell (Phoenix, AZ)
- As a Sr Advanced Software Engineer here at Honeywell, you will be responsible for designing, developing, and implementing innovative software solutions that drive ... DO-178B/C, ARP4754 + V&V experience for Design for Test ( DFT ). **You Must Have** + At least 6 years...chipsets, graphics pipeline, graphics drivers and display devices (SOC, CPU , GPU, FPGA) + Hands-on experience in development of… more