- Google (Portland, OR)
- …+ Contribute to CPU frontend designs, with emphasis on microarchitecture and RTL design for the next generation CPU . + Propose performance enhancing ... practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. + 3 years… more
- Google (Austin, TX)
- …at Google (https://careers.google.com/benefits/) . + Contribute to CPU front - end designs, emphasizing on microarchitecture and RTL design for the next ... practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. + Experience… more
- Cadence Design Systems, Inc. (Austin, TX)
- …block/IP success for all target specifications in Silicon Qualifications: 10+ years of Front End design and/or verification.with a BS/MS Engineering or Computer ... Rich experience in IP creation and/or SoC and IP ( CPU , Memory, Interface) integration Expert in RTL ...good communication and design management skills Experience with Cadence front end toolset #LI-MA1 We're doing work… more
- Qualcomm (Austin, TX)
- …various cross functional teams and external vendors. Collaborate with both CAD and front - end design teams in productizing solutions to enable faster and more ... **Company:** Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU DV Infrastructure… more
- Qualcomm (San Diego, CA)
- …the following:** + LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU , DSP, and multimedia processors ... interfaces to the rest of the system such as CPU , GPU, DSP, Multimedia Processors and the engineer is...Engineering, or related field. + 5+ years ASIC design, RTL coding, front - end digital design… more
- Qualcomm (San Diego, CA)
- …quality of results. **Experience with the following:** + DDR controller architectures especially the front end interfacing to the CPU , DSP, and multimedia ... for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces...interfaces to the rest of the system such as CPU , DSP, Multimedia Processors and the engineer is expected… more
- Cisco (San Jose, CA)
- …silicon validation tests in the lab. Who You'll Work With You will work with front - end RTL Design and Verification teams and Architects to understand chip ... an ASIC Engineering Technical Leader with primary focus on RTL Design. * Create micro-architecture specifications and participate in...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable. * Design experience with Ethernet MAC,… more
- Meta (Austin, TX)
- …with upcoming networking standards like UEC 18. Experience in developing PCIe based NICs, Front - end and Back- end NICs 19. Experience in developing networking ... on data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation… more
- quadric.io, Inc (Burlingame, CA)
- …Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU /GPU/ASIC front - end design + Proficiency in SystemC, SystemVerilog, or Verilog ... by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog...+ Contribute to timing closure through full product cycle ( front end , back- end , tapeout) Requirements:… more
- Meta (Austin, TX)
- …upcoming networking standards like UEC 19. Experience in developing PCIe based NICs, Front - end and Back- end NICs **Public Compensation:** $212,000/year to ... on data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation… more
- quadric.io, Inc (Burlingame, CA)
- … CPU /GPU/ASIC implementation + Proficiency in TCL scripting + Proficiency in chip front - end and back- end implementation tools such as Design Compiler, ... process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip… more