- Integense (Portland, OR)
- …STA, PnR, DFT and ATPG, extraction, etc. + Experience with pre-silicon RTL design verification , System Verilog or UVM /OVM/VMM, test bench creation, ... designs for best in class ATE products. Responsibilities: + Complete Ownership of the Digital Design and Verification for ATE products - full Front End and Back… more
- NVIDIA (Santa Clara, CA)
- …in Computer or Electrical Engineering (or equivalent experience). + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... automation, RTL integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and automation… more
- NVIDIA (Santa Clara, CA)
- … automation. + Excellent analytical and problem-solving skills. + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... automation, RTL integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and automation… more
- NVIDIA (Santa Clara, CA)
- … automation + Excellent analytical and problem-solving skills + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals with… more
- Microsoft Corporation (Mountain View, CA)
- …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... cloud servers, clients, and augmented reality. We are looking for a **Principal Design Verification Engineer** to work on leading edge IP (intellectual property)… more
- Qualcomm (San Diego, CA)
- …MS degree in Electrical Engineering or equivalent; 1 year of practical experience + Design Verification knowledge - UVM /System Verilog preferred + Knowledge ... IP integration and system-level debugging. + System level RTL simulation & design verification . + Support chip bring up and post silicon debug. + Debug… more
- BAE Systems (Nashua, NH)
- …skills (C/C ) + Scripting skills (Perl, Python, bash, Tcl) + Exposure to Design Verification methodologies such as UVM /OVM + Experience with Earned ... **Job Description** BAE Systems is seeking FPGA Design Managers! Because this role involves a combination...onsite and remotely. BAE Systems is seeking an FPGA Design Manager to work within our Electronic Systems business… more
- Echostar (Germantown, MD)
- …System View, or similar tools + Knowledge and understanding of digital hardware, FPGA design , and UVM verification techniques Will be eligible for ... at our headquarters in **Germantown, MD** . **Responsibilities** : + Design , simulate, implement, and test digital signal processing-based modems for satellite… more
- BAE Systems (Nashua, NH)
- …skills (C/C ) + Scripting skills (Perl, Python, bash, Tcl) + Exposure to Design Verification methodologies such as UVM /OVM + Experience with Earned ... leadership experience needed to manage a team of FPGA Designers and Design Verification engineers solving complex problems? Do you have the business acumen to… more
- NVIDIA (Santa Clara, CA)
- …in verification of design IP with SystemVerilog, advanced methodologies (such as UVM ), and design and verification tools (such as VCS or equivalent ... NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world's leading SoC's and GPU's. This position… more
- Lightmatter (Boston, MA)
- … to develop comprehensive test plans. + Design and implement UVM testbenches for both subsystem-level and full-chip verification . This includes debugging ... Sr. Staff Design Verification Engineer Lightmatter builds chips...Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to… more
- Lightmatter (Mountain View, CA)
- … to develop comprehensive test plans. + Design and implement UVM testbenches for both subsystem-level and full-chip verification . This includes debugging ... Sr. Design Verification Engineer Lightmatter builds chips...role will primarily involve close collaboration with our digital design experts, where you will utilize UVM … more
- Meta (Columbus, OH)
- …applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure...practical experience. 8. 5+ years of hands-on experience in SystemVerilog/ UVM methodology and/or C/C++ based verification . 9.… more
- Meta (Austin, TX)
- …applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure...13. Experience in development of UVM based verification environments from scratch 14. Experience with Design… more
- Meta (Sunnyvale, CA)
- …applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure...15. Experience in development of UVM based verification environments from scratch. 16. Experience with Design… more
- Qualcomm (Austin, TX)
- …based verification + Testbench Architecture and Implementation + Strong SV/ UVM knowledge + GPU Shader Subsystem exposure + Various types of reference ... GPU hardware, drivers, features, applications, and tools. + Creates and maintains verification testbenches and environments in Systemverilog/ UVM + Guide more… more
- Micron Technology, Inc. (Atlanta, GA)
- …DRAM circuit design and operation. + Familiarity with SystemVerilog testbench/ UVM /Constrained Random verification methodology is strong plus. + Proficient in ... world uses information to enrich life. Micron is searching for its next Principal/Senior Design Verification Engineer! In this role, you will work with a highly… more
- Meta (San Diego, CA)
- …Preferred Qualifications: 14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design verification ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology. 10. 5+ years… more
- Google (Mountain View, CA)
- …related field, or equivalent practical experience. + 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. + ... Learn more about benefits at Google (https://careers.google.com/benefits/) . + Plan the verification of digital design blocks by understanding the design… more
- Amazon (Boise, ID)
- …tablets, Fire TV and Amazon Echo. What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will be part of an advanced engineering and ... across multiple disciplines - Deliver detailed test plans for verification of complex digital design blocks by... engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and… more