- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing ... meet the specifications for system performance. + Work with design engineers by providing detailed floor plan...(or equivalent experience) + Minimum of 6 years of mask design / layout experience + Detailed… more
- NVIDIA (Santa Clara, CA)
- …human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior ... Mask Layout Design Engineer ! Someone who is excited to...+ You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.… more
- NVIDIA (Santa Clara, CA)
- …the world. This is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from ... you! We are looking for a Senior Mask Layout Design Engineer , someone...tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.… more
- NVIDIA (Santa Clara, CA)
- Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... Cadence tools + You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products...MSEE is a plus. + 8+ years of relevant mask design / layout experience + Tape-out… more
- NVIDIA (Santa Clara, CA)
- Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone ... with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high… more
- MIT Lincoln Laboratory (Lexington, MA)
- …the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout, material growth and characterization, ... as a member of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and… more
- MIT Lincoln Laboratory (Lexington, MA)
- …the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout, material growth and characterization, ... cell libraries, documenting code and methodology updates, and documenting layout changes. The engineer will collaborate with others involved in mask layout from… more
- Actalent (Camarillo, CA)
- …to handle small, fragile parts with tweezers. + Strong attention to detail. + Experience in mask design and with mask design software. + Program or ... InP, InGaAs, GaSb) used in the fabrication of infrared detector arrays. The engineer will be responsible for creating and implementing new processes, using design… more
- Fujifilm (Santa Clara, CA)
- …or ceramic dry etching (DRIE); wet etching; wafer bonding, or AutoCAD software for mask design . + Familiar with some statistic software and programming skills ... **Position Overview** The Quality Engineer (Fab) will develop and improve MEMS wafer...specifically on quality and yield improvement. Identify and investigate design /process/equipment issues that limit wafer yield. Manage production yield… more
- Siemens (Fremont, CA)
- …the adoption, proliferation, and successful production deployment of Calibre products from design through mask production. Provide support to our leading-node ... Req ID: 448935 Siemens EDA is a global leader in Electronic Design Automation (EDA) software, underpinning today's cutting-edge mobile communications, AI hardware,… more
- Skyworks (Irvine, CA)
- Mask Assembly Automation Engineering - Co-Op Apply now " Date:Apr 17, 2025 Location: Irvine, CA, US Company: Skyworks If you are looking for a challenging and ... are changing the way the world communicates. Requisition ID: 74869 Job Description Mask Assembly automation Summer/Fall Coop will be responsible for + Support and… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... with customers, program managers, other unit process engineers , and integration engineers during the design and execution of process development and… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... with customers, program managers, other unit process engineers , and integration engineers during the design and execution of process development and… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. Candidates must ... as experienced in coat defect resolution, film-thickness optimization, root-cause-analysis, and design of experiments. The Photolithography Engineer will be… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. Candidates must ... to communicate well with others as well as experience in root-cause-analysis, and design of experiments. The Photolithography Engineer will be responsible for:… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, testing, and assembly. **This is ... Interfacing with other unit process engineers , operations, and integration engineers during the design and execution of process/equipment improvement… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, testing, and assembly. **This is ... independent and resourceful Thermal or Plasma Enhanced CVD Process Engineer Process Engineer . Advanced Technology Lab (ATL)...other unit process engineers , operations, and integration engineers during the design and execution of… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, testing, and assembly. **This is ... Interfacing with other unit process engineers , operations, and integration engineers during the design and execution of process/equipment improvement… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... with customers, program managers, other unit process engineers , and integration engineers during the design and execution of process development and… more
- Northrop Grumman (Linthicum Heights, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The candidate ... talented, motivated, and creative 4th Shift **Physical Vapor Deposition (PVD)** **Process Engineer ** for our Advanced Technology Lab (ATL) - located outside of… more