• Senior Mask Layout Design

    NVIDIA (Santa Clara, CA)
    Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... BSEE or equivalent experience. MSEE is a plus. + 8+ years of relevant mask design / layout experience + Tape-out experience with FinFET technology is… more
    NVIDIA (04/13/25)
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  • Integrated Circuit (IC) Layout

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... and laying out devices, test structures, systems, and full mask reticles based on input from device and process...in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our… more
    MIT Lincoln Laboratory (05/29/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior ... Mask Layout Design Engineer! Someone who is excited to join a growing and multifaceted group of diverse individuals responsible for handling significant… more
    NVIDIA (04/24/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... a BSEE or equivalent experience. + Minimum of 7+ years industry experience in Mask and Layout Design . + Deep understanding of analog circuit layout more
    NVIDIA (04/17/25)
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  • Senior Mask Designer and CAD Engineer

    NVIDIA (Austin, TX)
    …creativity and intelligence. We would love to hear from you! We are seeking a Senior Mask Layout Design Engineer to join our growing and dynamic team. The ... + BSEE degree (or equivalent experience) + 7+ years of industry experience in Mask and Layout Design . + Deep understanding of layout concepts in… more
    NVIDIA (06/04/25)
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  • Lead Lithography Engineer

    IBM (Albany, NY)
    …* EUV Lithography (10yr) * Lithography roadmap for BEOL technology definition (5yr) * Test vehicle/ mask layout design (5yrs) IBM is committed to creating a ... is preferred. Familiarity with computational lithography (OPC/RET development) and test vehicle/ mask design is a plus. Generation of Intellectual Property… more
    IBM (05/15/25)
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  • Mask Layout Designer

    Cubic Corporation (Durham, NC)
    …IC or MEMS processes. + Proficiency using Design Workshop 2000 or similar mask layout tool is required. + Proficiency in running/modifying custom GPE scripts ... responsible for ensuring all PolyStrata(R) designs conform to documented layout procedures and design rules via DRC....via DRC. + Ensure the efficient operation of the mask design process. + Assist in development… more
    Cubic Corporation (05/26/25)
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  • Electronic-Photonic Process Design Kit…

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... changes. The engineer will collaborate with others involved in mask layout from basic layout ...o Programming in Perl, TCL, or Python o RF layout design experience o Experience with Cadence… more
    MIT Lincoln Laboratory (05/09/25)
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  • Mask Release Automation Engineer

    IBM (Albany, NY)
    …semiconductor test chip development. This cross-functional role bridges the gap between design automation and mask release operations, requiring a blend of ... data using internal automation tools for timely submission to mask houses. * Design Automation: Develop and...ICWB, Cadence Virtuoso, Cadence MaskCompose) with 3+ years of design experience * Familiarity with layout verification… more
    IBM (05/05/25)
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  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Mask Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... hardworking, creative, and highly motivated engineers to work on the physical layout design and development of our next generation custom SRAM macro-IPs. As part… more
    NVIDIA (06/10/25)
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  • Principal Engineer Microelectronic…

    Northrop Grumman (Manhattan Beach, CA)
    …the Northrop Grumman Microelectronics Center. Candidate will be primarily responsible for lithography mask layout using computer aided design (CAD) with ... Grumman Mission Systems has an opening for a Microelectronics Layout Engineer to join our team of qualified, diverse...location in Redondo Beach, CA. SPF is where we design , manufacture, and test semiconductor products for internal and… more
    Northrop Grumman (05/31/25)
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  • Senior Printed Circuit Board Layout

    OTTO Engineering (IL)
    Senior Printed Circuit Board Layout Designer - Communications OTTO's opportunity: Our Senior Printed Circuit Board Layout Designer will perform all aspects of ... Printed Circuit Design including creation and maintaining library components, collaborating with...understanding of schematics circuit functions is needed to implement layout strategies necessary for optimal ESD, EMC, Power and… more
    OTTO Engineering (03/27/25)
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  • Systems Administrator

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... and classified networks. The candidate will have experience in the design of computer system solutions, including provisioning, configuration, and management of… more
    MIT Lincoln Laboratory (05/27/25)
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  • Quantum Processor Design , Quantum AI

    Google (Goleta, CA)
    …experience working in a physics research environment utilizing software engineering tools for layout design and development. + Experience with Python or other ... years of experience working in physics research environment utilizing software engineering tools for layout design and development. + Knowledge of Layout vs … more
    Google (05/28/25)
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  • Quantum Hardware Design Engineer

    IBM (Yorktown Heights, NY)
    …hardware testsites * Connectivity/schematic capture for quantum hardware releases * Detailed mask layout and chip finishing for quantum hardware releases * ... experience (Ansys Electronics Desktop, Keysight Momentum, Cadence Clarity etc.) * Mask /PCB layout experience (Cadence Virtuoso, KLayout, Synopsys Custom… more
    IBM (05/28/25)
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  • Senior SRAM Engineer, Circuit Design

    NVIDIA (Santa Clara, CA)
    …circuits that help power these chips. What you'll be doing: + Design best-in-class SRAM circuits using state-of-the-art technology processes + Optimize circuits for ... performance, area, and power + Supervise mask designers to craft high quality and... designers to craft high quality and dense pitch-matched layout + Verify functionality, electrical integrity, and robustness +… more
    NVIDIA (06/03/25)
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  • Semiconductor Equipment Engineer / Principal…

    Northrop Grumman (Linthicum Heights, MD)
    …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... Lab (ATL) - located outside of Baltimore, Maryland - where we design , manufacture, and test semiconductor products for internal and commercial production customers… more
    Northrop Grumman (06/04/25)
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  • Sr Principal Engineer Microelectronic…

    Northrop Grumman (Apopka, FL)
    …Engineer will lead and manage engineering projects such as equipment layout , cleanroom construction, and installation of semiconductor equipment, along with the ... and Responsibilities:_** + _Maintain all aspects of facilities and factory layout for foundry equipment._ + _Develop and apply continuous improvement programs… more
    Northrop Grumman (05/14/25)
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  • Senior Principal Semiconductor Lithography…

    Northrop Grumman (Linthicum Heights, MD)
    …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The ... Lab (ATL) - located outside of Baltimore, Maryland - where we design , manufacture, and test semiconductor products for internal and commercial production customers… more
    Northrop Grumman (05/08/25)
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  • Director, Engineering

    Skyworks (Irvine, CA)
    …the best BAW stack design solution. * Work with process development team to design Process Development Vehicle mask layout for a new technology and ... Product Engineering, R&D Engineers, Process experts, Filter and Module Design Team, and Operations in US, Korea, and Japan....mitigation plans with NPI engineering team. * Work with design engineering and assist to identify the key performance… more
    Skyworks (05/31/25)
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