- SanDisk (Milpitas, CA)
- …keep our world moving forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from ... REQUIRED: + **Experience:** A minimum of 3 years in Physical design digital RTL to GDS flow....**EDA Tools:** Familiarity with Cadence, Synopsys digital flow include Synthesis , PNR, STA. Calibre physical verification, Redhawk… more
- Silvus Technologies (Los Angeles, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA ... using Verilog and System-Verilog. + Proven expertise working with front-end RTL design tools, FPGA synthesis , timing closure, multiple clock-domain and/or… more
- Micron Technology, Inc. (Folsom, CA)
- …in Folsom, California is seeking a highly experienced **Custom Layout and High-Speed I/O Design Engineer ** to help shape the future of memory solutions for AI ... Micron's industry-leading HBM product family. **Responsibilities** + Own full-chip floorplanning, design partitioning, and top-level synthesis with multiple hard… more
- Silvus Technologies (Los Angeles, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Teradyne (North Reading, MA)
- …business results. Opportunity Overview Our Hardware Engineering team is seeking an FPGA/ASIC Design Engineer to work with a multi-disciplined team to design ... digital simulation tools to verify designs. + Creation of physical design constraints for placement, timing closure...CDC + Implementation of designs into target technologies using synthesis and place and route tools + Perform timing… more
- SanDisk (Milpitas, CA)
- …and full chip circuit simulations to meet all performance specifications. + RTL design , synthesis , static timing analysis and verification in verilog for page ... an exciting opportunity for you. ESSENTIAL DUTIES AND RESPONSIBILITIES: + Architect and design circuits at transistor level and gate level for leading-edge 3D NAND… more
- Micron Technology, Inc. (Folsom, CA)
- …HBM RTL designer will need to have significant experience front end digital design ! The designer will be responsible for the development several blocks. Development ... specifications, architecting, being responsible for circuit development, simulations, guiding physical layout, and driving validation. **Responsibilities** + Define requirements,… more
- SpaceX (Sunnyvale, CA)
- …work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. SOC/ASIC Physical Design Methodology/CAD Engineer ...EXPERIENCE: + Experience in high-performance, low-power physical design , and implementation techniques with industry standard synthesis… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... in EE/CS - 5+ years developing physical design methodology or CAD flows in synthesis ,...languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis… more
- Texas Instruments (Santa Clara, CA)
- …IR-drop, EM-checks, physical verification such as DRC, LVS, Antenna etc. As a physical design engineer , you will be responsible for tapeout in ... and high-speed interfaces to Analog. Your responsibilities will include synthesis , various steps of physical design...groups, providing ideas and collaborative teamwork. **Why TI?** + Engineer your future. We empower our employees to truly… more
- Cisco (Maynard, MA)
- …in developing and optimizing physical floorplan and their implementation. Your Impact The Physical Design Engineer Co-op will perform one or more of the ... to understand the design architecture to ensure optimal physical implementation . Gate level netlist synthesis ( physical synthesis ) . Physical … more
- Amazon (Austin, TX)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... tradeoffs for physical design closure - Drive IO/Core block physical implementation through synthesis , floor planning, bus / pin planning, place and… more
- SpaceX (Sunnyvale, CA)
- Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
- Amazon (Austin, TX)
- …of machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our ... ASIC physical design , physical design flows, and methodologies including synthesis , place and route, STA, formal verification. - Proven track record… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... on-chip interconnect network and last-level caches , working closely with the physical design team on implementation, synthesis and timing closure as well… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,...including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure... implementation of multi-hierarchy low-power and high-performance designs, including physical -aware logic synthesis , floorplan, place and route,… more
- Google (Mountain View, CA)
- Senior CPU Physical Design Engineer , Silicon...+ 5 years of experience with physical design flow such as constraints, synthesis , floor ... and route, clock tree synthesis (CTS), or physical verification. + Experience in one or more sign-off...drive architectural feasibility studies, and identify power-performance-area tradeoffs for physical design closure. + Drive block/IP … more
- Northrop Grumman (Annapolis Junction, MD)
- …of our mission! Northrop Grumman Mission Systems (NGMS) is seeking a Sr. Staff ASIC Physical Design Engineer to support our growing engineering team in ... implementation at both block and chip levels. + Perform physical design of ASIC designs, including floor...designs, including floor planning, placement and routing, clock tree synthesis , physical verification, and IR/EM analysis. +… more
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