- Qualcomm (San Diego, CA)
- …define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and ... RTL design team to develop timing constraints, drive implementation of the designs to meet...STA correlation. + Find out the root cause of timing miscorrelation at different design levels in… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing ...and guide them in refining design and timing constraints for seamless physical design ... of what's possible! **Your Impact** You are a diligent Design /SDC Engineer with strong analytical skills and...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- Qualcomm (Santa Clara, CA)
- …crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements ... and bottlenecks. + Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. + Review and… more
- Qualcomm (San Diego, CA)
- …of timing bottlenecks and mitigation solutions. + Guidance to front-end and physical teams on all aspects of timing considerations. + Development and support ... latest DDR technologies. This position requires involvement in static timing analysis (STA) and closure of DDR PHY interface...integration aspects for DDR PHYs. + Good understanding of design for yield and production challenges with DDR systems.… more
- Qualcomm (San Diego, CA)
- …in 5nm, 4nm and beyond (process technologies). + You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and ... Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital...have good execution knowledge. + Your contribution should improve timing convergence process across the company, design … more
- Northrop Grumman (Morrisville, NC)
- …+ Work closely with design , verification, design -for-test and physical design teams to optimize the timing and improve design performance + ... Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of...maintain timing methodologies and flows for efficient timing analysis and closure + Conduct design … more
- Microsoft Corporation (Redmond, WA)
- …semiconductor designs. + Collaborate with design , implementation, and physical design teams to define and drive timing constraints and methodology. + ... the Cloud infrastructure. We are looking for a **Principal Timing /STA Engineer ** to join the team. **Responsibilities**...OR equivalent experience. + 8+ years of experience in Physical Design , specifically Static Timing … more
- NVIDIA (Santa Clara, CA)
- …Electrical or Computer Engineering or equivalent experience. + 8+ years experience in Physical design / Timing . + Experience in full-chip/sub-chip Static ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- NVIDIA (Santa Clara, CA)
- …crossing of clock domains across hierarchical boundaries). + Collaborate with RTL, physical design , and verification teams to drive consistency and correctness ... inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to...or Computer Engineering with 4+ years' experience in ASIC Design and Timing . + Expertise in Primetime… more
- Google (Sunnyvale, CA)
- …+ Experience writing, reviewing and verifying complex TCL constraints for static timing analysis. + Experience in extraction of design parameters, QoR ... benefits at Google (https://careers.google.com/benefits/) . + Debug and resolve common Static Timing Analysis (STA) or design rule issues like unconstrained… more
- NVIDIA (Santa Clara, CA)
- …skills and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out ... or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and timing… more
- NVIDIA (Westford, MA)
- …impact in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team,… more
- Qualcomm (San Diego, CA)
- …and develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading ... the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... first customer shipments **Your Impact** You are a diligent Design /SDC Engineer with strong analytical skills and...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- Qualcomm (San Diego, CA)
- …Perl & experience in developing large scale automation from scratch. + Experience in STA, physical design is a plus. + Experience of spice simulation models, ... experience with industry standard chip design tools and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power… more
- Capgemini (CO)
- …to automate design flows and analysis tasks. + Hands-on experience with physical design implementation is a plus. + Excellent communication skills, with the ... Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior Physical Design Engineer_ **Location:** _Colorado_ **Requisition ID:** _080209_ more
- NVIDIA (Austin, TX)
- …in PrimeTime, PrimeTime-PX, NanoTime, SPICE, or other analysis tools + Background in physical design , timing , and/or power optimization algorithms. + ... algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale...time, this role can expand to other areas of physical design implementation and analysis tools +… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding... design and implementation. + Hands-on experience in physical synthesis, floor planning, P&R, and timing … more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
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