- Marvell Technology, Inc. (Westborough, MA)
- …Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Physical Design Engineer at Marvell Technology, you will be a key part ... physical design flow for Marvell's high-performance, cutting-edge chips. You'll work on synthesis , place and route, and timing analysis for intermediate and complex… more
- Amazon (Portland, OR)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
- NVIDIA (Santa Clara, CA)
- …methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs ... , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design, formal equivalence checking. + Proven track...ASIC methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... + Help in driving frontend and backend implementation including synthesis , equivalence checking, floor-planning, timing constraints, timing and power convergence,… more
- NVIDIA (Westford, MA)
- …to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. + Help in driving… more
- Microsoft Corporation (Austin, TX)
- …that will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Fabric Design** ** Engineer ** to join the team. **Responsibilities** + Be ... standard interface protocols such as AXI or CHI. + Familiarity with Synthesis and STA tools. + Good verbal and written communication skills. Silicon Engineering… more
- L3Harris (Camden, NJ)
- …in the interest of national security. Job Title: Sr ASIC/FPGA VHDL Design Engineer Job Code: 24260 Job Location: Camden, NJ-relocation available for those that ... Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part...RTL (VHDL) and perform module level simulations + Perform Synthesis , Place and Route (PAR) and Static Timing Analysis… more
- Microsoft Corporation (Santa Clara, CA)
- …to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex ... of industry experience as a Design For Test (DFT) engineer . + Hands on experience with Tessent tools for...System Test structures + Experience with Synopsys tools for synthesis and STA + Experience with System… more
- Amazon (Cupertino, CA)
- …Python, C++) - Solid understanding of ASIC physical design, and methodologies including synthesis , place and route, STA , IR, formal and physical verification. - ... of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated to ... management to ensure compatibility between all workflows. + Run synthesis workflows and optimize for area, power, and timing....Run physical design flow from netlist to GDS, perform STA , physical verification (LVS/DRC) + Perform netlist checks and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... with architects, platform, and software teams. + Partner with design, verification, synthesis , timing, and backend teams to ensure cohesive integration. + Create and… more
- NVIDIA (Santa Clara, CA)
- …3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs. + Strong background ... flows and methodologies. + Familiarity with methodology and tools, logic synthesis , equivalence checking. + Strong interpersonal and communication skills and ability… more
- NVIDIA (Santa Clara, CA)
- …advanced Clock tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation + Good understanding of design rules in ... advanced nodes and their impact on DRC closure and PPA optimization + Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design, pinning and budgeting flows + Experience with power… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base ... Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg synthesis ,… more
- L3Harris (Orlando, FL)
- …Job Code: 25783 Job Location: Orlando, FL Schedule: 9/80 - Onsite Job Description: The Senior Digital Design Engineer will be a key member of the ALST ... simulation test bench development, simultation testcase coding, Static Timing Analysis ( STA ), power consumption estimation, FPGA synthesis , FPGA place and… more
- SanDisk (Milpitas, CA)
- …NAND flash, including new, most advanced 3-dimentional NAND memories. A design engineer will focus on developing technologies related to AI. In this role, ... **Physical Design Engineering** - Physical Design Engineers will be responsible for logic synthesis , place and route (P&R), and timing analysis for NAND flash memory… more
- Samsung Electronics Co., Ltd. (Austin, TX)
- …the world. Come build with us! Role and Responsibilities As a Senior Coherent Interconnect Micro-Architect, you will be responsible for leading the ... and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. + You drive the… more