- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing ... related field (or equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. + Strong expertise in… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place… more
- Cisco (Maynard, MA)
- Senior ASIC Timing Engineer Apply...a highly team focused environment. + Involves in static timing analysis (STA) methodology and flow. Including but ... timing technologies, like latest on-chip variation modeling techniques, PVT selection, extraction methodology and flow, etc. + Run signoff timing analysis at… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... with multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Engineer in Custom Timing to join our dynamic and growing team. If you are looking for a challenging and ... performance and reliability of Nvidia's next generation products. + Develop timing models and methodology for custom macro design at transistor level along with… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, ... GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...and improve existing flows and methodologies. + Familiarity with methodology and tools, logic synthesis, equivalence checking. + Strong… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion ... improve PPA + Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our ... equivalent experience + 3+ years of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our ... for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- NVIDIA (Santa Clara, CA)
- …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... equivalent. + Strong fundamentals in digital design, system and microarchitecture, timing , clocking, power, noise, and control systems; Deep understanding of… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...optimization tasks + Collaboration with physical design to address timing , area, congestion tradeoffs + Drive timing … more
- RTX Corporation (Cedar Rapids, IA)
- …position is for a highly experienced, highly motivated Electrical or Computer Engineer that will be involved in the design, implementation, verification and ... of high-performance ASICs, FPGAs, and SoPCs for Collins Avionics solutions. As an engineer in this organization, you will be employing best practice design and… more
- The Hartford (Charlotte, NC)
- …Enterprise Data Services department's IT team supporting Global specialty is seeking a hands-on Senior Staff Data Engineer to enhance and support its Data assets ... OH) 3 days a week (Tuesday through Thursday). The Senior Staff Data Engineer will be proficient...data Masking. + Have a solid understanding of delivery methodology (SDLC) and lead teams in the implementation of the… more
- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Renesas (Duluth, GA)
- Senior Staff Digital Engineer Job Description + **Education:** Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or ... + Fluent in Verilog RTL coding and ASIC design methodology + Expertise in digital design implementation, including logical...DFT insertion with high coverage + Experience with static timing analysis and creation of place and route constraints… more