- NVIDIA (Santa Clara, CA)
- …bringup to product release. Our ArchDev arm is a hub for all silicon and system-level feature development , ROI analysis, system integration solutions, and ... team, you will be responsible for championing and architecting silicon cross-IP power savings features with a...telemetry of key product use cases to drive the development of new features with the highest return and… more
- Microsoft Corporation (Santa Clara, CA)
- … team and be responsible for delivering cutting-edge, high performance, low power , scalable and programmable DPU silicon . **Responsibilities** + As a Senior ... Microsoft Silicon , Cloud Hardware, and Infrastructure Engineering (SCHIE) is... latency, high bandwidth) design techniques + Understanding of low power microarchitecture techniques. Knowledge of Verilog,… more
- Microsoft Corporation (Santa Clara, CA)
- …and be responsible for delivering cutting-edge, high performance, low power , scalable and programmable DPU silicon . \#azurehwjobs **Responsibilities** As a ... Microsoft Silicon , Cloud Hardware, and Infrastructure Engineering (SCHIE) is... latency, high bandwidth) design techniques + Understanding of low power microarchitecture techniques. Knowledge of Verilog,… more
- Microsoft Corporation (Santa Clara, CA)
- …team and be responsible for delivering cutting-edge, high performance, low power , scalable and programmable DPU silicon . **Responsibilities** + As a ... Microsoft Silicon , Cloud Hardware, and Infrastructure Engineering (SCHIE) is... latency, high bandwidth) design techniques + Understanding of low power microarchitecture techniques. knowledge of Verilog,… more
- Microsoft Corporation (Hillsboro, OR)
- …equivalence failures. + Perform cross-functional decision making across UPF (Unified Power Format)/ Low Power methodology/architecture, DFT methodology, ... DFT methodology and handling DFT constraints for Logical Equivalence + Timing Constraints/ Low Power Static verification flows to augment pure functional… more
- Microsoft Corporation (Raleigh, NC)
- …+ Design release packaging and qualification, RTL quality flows, static checks. + Low Power design. **Other Requirements** Ability to meet Microsoft, customer ... The Microsoft Silicon Engineering and Solutions Team is looking to.../Unified Power Format (UPF) linting flows like Power Artist/Jules, Verification Checks Low Power… more
- SpaceX (Irvine, CA)
- … silicon process and technology nodes for high speed and low power consumption + Software design and development skills + Excellent scripting skills ... Sr. SoC Implementation Engineer ( Silicon Engineering) at SpaceX Irvine, CA SpaceX was...to solve complex problems including clock domain crossings and power optimization + ASIC/SoC system integration experience + Experience… more
- Google (Mountain View, CA)
- …+ 4 years of experience in people management, leading IP/SoC design team for low power SoCs. + Experience with ARM-based SoCs, interconnects, and ASIC ... design for clocking, interconnects, and peripherals. + Experience with methodologies for low power estimation, timing closure, and synthesis. + Experience… more
- Google (San Diego, CA)
- …SIPI, Design for Manufacturing (DFM) and limited production. + Experience in intricate power delivery network design for low voltage and high current rails ... experience in design and bring-up of hardware for post silicon validation of SoCs. + Experience driving HDI and...with signal and power integrity concepts. + Experience with electrical parameters for… more
- SpaceX (Sunnyvale, CA)
- … power intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified ... physical design implementation and STA Signoff + Experience with power intent and upf development for block...flow, top-down and bottom-up design methodologies + Knowledge of low - power methodologies and leakage/dynamic power … more
- Meta (Sunnyvale, CA)
- …Algorithms that combine ML and 'classic' processing that are optimizing performance at low power 3. Develop software including functional model and bit accurate ... an architect specializing in multimedia algorithms (Graphics, Imaging, Computer Vision) for Silicon Acceleration. The role requires knowledge in both classic and ML… more
- SpaceX (Redmond, WA)
- …all aspects of implementation in the system. + Simulate/model MMIC front end circuits ( power amplifiers, low noise amplifiers, switches) at the circuit level and ... Sr. MMIC Design Engineer ( Silicon Engineering) at SpaceX Redmond, WA SpaceX was...MMIC design of linear and non-linear circuits such as power amplifiers, low noise amplifiers, mixers, filters… more
- Amazon (Austin, TX)
- Description AWS-Annapurna develop the silicon used in our most advanced machine learning accelerator servers, utilizing cutting edge process nodes and massively ... classic ATE platforms to create a clean running extremely low DPPM product-line forming the foundation to our servers....our final product is a server, not just the silicon , you will find yourself stretching beyond structural testing… more
- SpaceX (Redmond, WA)
- …theory + Experience with design of linear and non-linear circuits such as power amplifiers, low noise amplifiers, mixers, filters and PLLs + Thorough ... Sr. RF/Microwave Engineer ( Silicon Engineering) at SpaceX Redmond, WA SpaceX was...and analyze full radio performance + Assist in the development of automated test equipment for lab measurements +… more
- Google (Mountain View, CA)
- …+ Experience with logic synthesis techniques to optimize RTL code, performance, and power , as well as low - power design techniques. Preferred qualifications: ... on computer architecture. + Knowledge of high performance and low - power design techniques. + Knowledge of ASIC...this role, you will work on design and RTL development of security features and sub-systems and their integration… more
- Qualcomm (San Diego, CA)
- …fast-paced SoC team responsible for development of next Generation, high performance, low power Memory Subsystem RTL Design, flows and methodology for high ... excellent analytical and technical skills, and a focus on low power , high performance ASIC designs, and,...power data to other cross-functional teams. + Build power models based on pre- silicon power… more
- Qualcomm (San Diego, CA)
- …register, logic, memory, and clock power + Develop and maintain tests for pre- silicon and post- silicon power verifications. + Work closely with multiple ... experience with ASIC design and verification + 4+ years of experience with low - power ASIC optimization **Preferred Qualifications:** + Master's or PhD degree or… more
- Amazon (Austin, TX)
- …vector and vectorless power analysis to get accurate average and peak power numbers during SoC development Working with emulation and application software ... get application specific power numbers using emulation power analysis flows during the SoC development ...package, PCB, and system Using lab equipment to perform power validation on new silicon and correlation… more
- Insight Global (Cleveland, OH)
- Job Description Day to Day: * Insight Global is seeking a ServiceNow ( Low Code) Engineer for one of our largest clients. Our client is looking for someone who ... ServiceNow applications and services. This person must have a software development background in addition to ServiceNow system administration, scripting in… more
- Qualcomm (Raleigh, NC)
- … design, power management products and voltage regulator (VR) selection, development , programming, debug, as well as post- silicon board/SoC test validation ... engineering disciplines: power electronics (switch mode and linear), power management, high bandwidth/ low latency control interfaces, thermal analysis,… more