- SpaceX (Bastrop, TX)
- Sr. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)… more
- SpaceX (Irvine, CA)
- SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... this possible, with the ultimate goal of enabling human life on Mars. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)… more
- SpaceX (Bastrop, TX)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- SpaceX (Sunnyvale, CA)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- Google (San Diego, CA)
- …for delivering System-on-Chip ( SoC ) Static Timing Analysis. + Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs. ... silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing...chip STA, timing ECO creation, and final timing signoff for SoC 's. Google… more
- Meta (Austin, TX)
- …and audits for IP and SOC development milestones including TO, from a timing signoff perspective. 4. Develop robust timing signoff automation ... ASIC Engineer, Methodology Responsibilities: 1. Work with our ASIC vendor partners and Foundries to assess signoff...development. 12. Experience with IP modeling and integration into SOC from a timing / signoff perspective.… more
- Meta (Sunnyvale, CA)
- … Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC . 8. Analyze the inter-block timing and come up with IO budgets ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...Timing /physical libraries, SRAM Memories. 22. Knowledge of STA signoff and understanding of AOCV, POCV 23. Experience with… more
- Meta (Sunnyvale, CA)
- … Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC . Analyze the inter-block timing and come up with IO budgets for ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...Timing /physical libraries, SRAM Memories. 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with… more
- Meta (Austin, TX)
- …tools 10. Experience with Lint, Clock Domain & Reset Domain crossing. 11. Experience with SOC CDC signoff 12. Knowledge of SOC Integration (Clocking, Reset, ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip… more
- Qualcomm (Austin, TX)
- …and integrate HM constraints into SoC and ensure correlation between HM and SoC timing . + Analyze timing across modes and corners, understand concepts ... for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate...validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. +… more
- Google (Sunnyvale, CA)
- …clock distribution circuits. + Experience in Spice simulations, clock verification, and signoff . Preferred qualifications: + Experience in ASIC physical design, ... flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data Capture (CDC),...Law in advanced technology nodes and deliver cutting edge ASIC 's and SoC 's. You will drive block… more
- Cisco (San Jose, CA)
- …bump and rdl planning, power grid design to clock planning, routing, and timing closure. * Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, ... provide solutions and ensure signoff clean results. * Work closely with block and...Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification * Experience in deep… more
Locations:
California,
Texas