• Senior ASIC Physical Design Engineer, Cache…

    NVIDIA (Santa Clara, CA)
    As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and ... timing closure while collaborating closely with the logic design team on micro -architecture definition and feasibility. This position offers you the opportunity to… more
    NVIDIA (11/20/25)
    - Save Job - Related Jobs - Block Source