- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Micron Technology, Inc. (Boise, ID)
- …inspiring the world to learn, communicate and advance faster than ever. As a Design Verification Engineer at Micron, you will work with a highly innovative ... and motivated design and verification team using groundbreaking memory...verification languages (System Verilog or equivalent) and methodologies ( UVM or equivalent) and other scripting languages (python, perl,… more
- Micron Technology, Inc. (Richardson, TX)
- …revisions + Simulate and verify designs using tools like FineSim/HSPICE and SystemVerilog / UVM + Build golden models and run corner/Monte Carlo analyses ... Engineering, Test/Probe, Process Integration, Assembly, and Marketing + Standardize and automate design checks and flows with CAD and verification teams +… more
- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- NVIDIA (Austin, TX)
- …design verification experience + Experience in pre-silicon verification ( UVM , SystemVerilog ), ASIC design /implementation flow, and design ... components using SV/ UVM methodology + Driving coverage-based verification closure + Collaborate with design teams...the crowd: + Previous experience automating tasks in the design verification process + Hands on experience… more
- Data Device Corporation (Bohemia, NY)
- …inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: Proficiency in Xilinx Vivado required; ... involves developing robust testbenches, creating advanced simulation environments, executing verification suites, and collaborating closely with Design Engineers… more
- Google (Mountain View, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... Senior Design Verification Engineer, Silicon _corporate_fare_ Google...Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
- Meta (Austin, TX)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Capgemini (Seattle, WA)
- …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
- Northrop Grumman (Annapolis Junction, MD)
- …The Systems Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies ... verification processes. **Role And Responsibilities:** The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification … more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- BAE Systems (Nashua, NH)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- Northrop Grumman (Linthicum Heights, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting...with Polygraph. + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience Northrop… more
- Meta (Sunnyvale, CA)
- …test cases using industry-standard verification languages and methodologies (eg 4. SystemVerilog , UVM ). 5. Perform simulation and debugging of ASIC designs ... 2. Collaborate with design engineers to understand design intent and identify potential verification challenges....languages (eg Verilog) and verification languages (eg SystemVerilog ) with in UVM (Universal Verification… more
- Google (Mountain View, CA)
- …scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or formally ... Design Verification Engineer _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more… more
- The Boeing Company (El Segundo, CA)
- …sites. **Position Responsibilities:** + Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. + Develop self-checking ... of the Boeing product line - approximately half our design / verification work is within the Space &...+ Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog / UVM , including the… more
