• SOC /ASIC Synthesis & Front-End STA

    SpaceX (Sunnyvale, CA)
    SOC /ASIC Synthesis & Front-End STA Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...and timing closure + Work closely with chip architecture, design verification, physical design , DFT,… more
    SpaceX (05/09/24)
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  • Sr. SOC Design Engineer - STA

    Amazon (Sunnyvale, CA)
    …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . - Streamlining the timing signoff criterions, timing analysis...- Should be able to work closely with IP Design teams and Backend Physical Design more
    Amazon (05/28/24)
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  • Synthesis/ STA Engineer

    Qualcomm (Santa Clara, CA)
    …future for all. As a Qualcomm Hardware Engineer, you will plan, design , optimize, verify, and test electronic systems. Qualcomm Hardware Engineers collaborate with ... of Qualcomm Connectivity organization responsible for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state… more
    Qualcomm (04/18/24)
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  • Principal SOC /ASIC Physical

    SpaceX (Sunnyvale, CA)
    Principal SOC /ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... ultimate goal of enabling human life on Mars. PRINCIPAL SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON...and fix signoff closure issues in static timing analysis ( STA ), noise, logic equivalency, physical verification, electromigration… more
    SpaceX (05/17/24)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    …that goes into our cutting-edge data centers affecting millions of Google users. As a SoC Physical Design Engineer, you will collaborate with Functional ... equivalent practical experience. + 4 years of experience with physical design flow such as floor planning,...design areas such as synthesis, place and route, STA , formal verification, or power analysis. Preferred qualifications: +… more
    Google (05/11/24)
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  • SoC Integration Engineer - Onsite

    ManpowerGroup (San Jose, CA)
    …engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design , verification, physical design , emulation and firmware. We use ... **We Are:** The Silicon Design group is a diverse team of world...an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can… more
    ManpowerGroup (03/22/24)
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  • Silicon Physical Design Engineer

    Actalent (Sunnyvale, CA)
    …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. About ... STA for the blocks and the top-level including SOC . Analyze the inter-block timing and come up with...Methodology for all FE-tools including Lint CDC RDC Synthesis STA Power. + Work closely with the Design more
    Actalent (05/18/24)
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  • NoC Interconnect Design Engineer…

    Qualcomm (Santa Clara, CA)
    …drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best ... should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design , and successful industry experience with deployment of IPs in large SoC more
    Qualcomm (04/10/24)
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  • 3D IC Solutions Engineer- Chiplet Design

    Siemens Digital Industries Software (Fremont, CA)
    …leading EDA and MCAD tools that facilitate the architectural planning, physical design /verification, muti-die based electrical, thermal, mechanical stress ... place and route engineering team to develop an integrated silicon interposer physical design and verification flow. Additional responsibilities include providing… more
    Siemens Digital Industries Software (05/25/24)
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  • 3D IC Solutions Engineer- DFT Design

    Siemens Digital Industries Software (Fremont, CA)
    …leading EDA and MCAD tools that facilitate the architectural planning, physical design /verification, muti-die based electrical, thermal, mechanical stress ... in developing test strategies and solutions for integrated Silicon-on-Chip ( SOC ) IP including PVT, thermal, stress and aging sensors...and design methods a plus: o RTL Design /Verification, Logic Syntheses, LEC, STA analysis o… more
    Siemens Digital Industries Software (05/30/24)
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  • 3D IC Solutions Engineer- Package Design

    Siemens Digital Industries Software (Fremont, CA)
    …methodology from RTL Synthesis to Physical Implementation phases o RTL Design /Verification, LEC, STA analysis o Integration and validation of Silicon-on-Chip ... leading EDA and MCAD tools that facilitate the architectural planning, physical design /verification, muti-die based electrical, thermal, mechanical stress… more
    Siemens Digital Industries Software (05/26/24)
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  • Senior DFT Engineer

    Qualcomm (San Jose, CA)
    …Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ... implementation and verification of DFT/DFD ( Design for Test/ Design for Debug) techniques for...propose best compression that can be achieved for given SoC /core/block + Own and deliver scan insertion, validate equivalence… more
    Qualcomm (04/18/24)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …experience in ASIC Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full ... plans for NVIDIA's next generation of CPU, GPU or SOC designs. + Owning STA of large...of RTL/logic design skills as well as physical design /circuit skills for timing closure. +… more
    NVIDIA (04/16/24)
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  • 3D IC Solutions Engineer- Thermal/Stress Engineer

    Siemens Digital Industries Software (Fremont, CA)
    …leading EDA and MCAD tools that facilitate the architectural planning, physical design /verification, muti-die based electrical, thermal, mechanical stress ... workflows will support predictive analysis during the architectural planning and analysis phase, in- design analysis during the physical design phase and… more
    Siemens Digital Industries Software (05/30/24)
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  • ASIC Architect

    Micron Technology, Inc. (San Jose, CA)
    …You should have strong knowledge and experience with many aspects of the SOC design and implementation flow - such as coverage-driven verification, synthesis, ... of its component IPs. + Defining requirements for ASIC design , verification, and physical implementation teams +...Verilog/SystemVerilog + Knowledge and experience in various aspects of SOC design , verification, and implementation flows +… more
    Micron Technology, Inc. (05/17/24)
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  • 3D IC Solutions Engineer- Technical Lead

    Siemens Digital Industries Software (Fremont, CA)
    …methodology from RTL Synthesis to Physical Implementation phases o RTL Design /Verification, LEC, STA analysis o Integration and validation of Silicon-on-Chip ... leading EDA and MCAD tools that facilitate the architectural planning, physical design /verification, muti-die based electrical, thermal, mechanical stress… more
    Siemens Digital Industries Software (05/26/24)
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  • Senior ASIC Engineer, Timing

    NVIDIA (Santa Clara, CA)
    …amplify human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block ... quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence,...timing issues, timing constraints and clocking. + Expertise in STA tools and methodologies for timing closure with a… more
    NVIDIA (04/18/24)
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