- NVIDIA (Santa Clara, CA)
- … engineer , you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: + Work as ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
- NVIDIA (Santa Clara, CA)
- …by leading cross-functional teams using the 8D process. Lead failure analysis activities including chip -level ATE, System level test (SLT) and Si FA tasks. + ... Servers, Visual Computing, Home Entertainment, Datacenters, Servers, Automotive, Embedded Systems , and more. This is a once in lifetime...Experienced in test equipment bring up + Familiar with system level test + Exposure to digital design… more
- NVIDIA (Santa Clara, CA)
- …and problem-solving skills. + Experience in RTL design (Verilog), verification (UVM, System Verilog), System -On- Chip design /integration flow, and ... footprint that is responsible to our environment. The NVIDIA System -On- Chip (SOC) group is looking for a...ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and… more
- NVIDIA (Santa Clara, CA)
- …SOC Design (SOCD) team is looking for a highly motivated and creative design automation engineer . As someone who is passionate about design automation, ... engineers to improve efficiency and productivity in our front-end chip development process through innovative design automation... automation solutions and practices + Define and develop system -level methodologies and tools to build SOCs in an… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- ASIC Design Engineer Job ID 5683 Location...signal design to implement the next generation system -on- chip (SoC) ASICs. As mixed signal designer ... SLAC National Accelerator Laboratory seeks an Application Specific Integrated Circuit (ASIC) design engineer within the Integrated Circuits Department of the… more
- Microsoft Corporation (Mountain View, CA)
- …clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic Microsoft Artificial Intelligence ... System on Chip (AISoC) Silicon team. As...design flows and methodologies for our cutting edge chip productions. Throughout the program you will be interacting… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer , you will be a ... MS in EE with 8+ years of experience in Digital Implementation, either as a design engineer or as a product engineer Strong understanding of VLSI physical … more
- Meta (Menlo Park, CA)
- …Silicon Packaging Design Engineer Responsibilities: 1. Perform package design for advanced custom silicon comprising single- chip /multi- chip and 3D ... **Summary:** Meta is looking for an experienced Silicon Packaging design Engineer for its Ecosystem and Technical...and analyses, package design /layouts based on silicon chip IO, electrical performance and system ID/form… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System -On- Chip devices, IP and complete systems at lower costs ... an impact on the world of technology. Successful applicant will participate in the design and development of a fully configurable and fully featured Network on … more
- Siemens Digital Industries Software (Fremont, CA)
- …technology and physics to deliver better products in the increasingly complex world of chip , board, and system design . **Position Overview** Fast. Reliable. ... system level * Facilitate discussions with individual users, design teams, and CAD teams to reach a common... and solutions, especially in the area of digital design and chip assembly. Identify opportunities and… more
- Meta (Sunnyvale, CA)
- …AR/VR silicon solutions in support of our industry leading virtual and augmented reality systems .As a Design Verification Engineer (DVEs), you will be a ... to drive our industry leading virtual and augmented reality systems . **Required Skills:** Design Verification Engineer...from IP to SoC level. 2. Provide feedback on IP/sub- system micro-architecture and RTL design . 3. Provide… more
- Google (Sunnyvale, CA)
- …computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high ... Google's services. As a Hardware Engineer , you design and build the systems that are...verification, physical verification, and power integrity. + Collaborate with chip design teams to implement flows and… more
- SpaceX (Sunnyvale, CA)
- … engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design , validation, product engineering). In this ... Design Verification Engineer (Silicon Engineering) at...with scripting languages, eg Python for automation + RTL design , chip bring-up, and post-silicon validation experience… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... in VLSI and/or Computer Architecture. + Experience in Verilog, System Verilog or similar HVL + Experience with CAD...or similar HVL + Experience with CAD and physical design methodologies (flow and tool development), chip … more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a ... - Full chip timing constraints development, full chip / Sub- System STA and Signoff for...STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal,… more
- Google (Sunnyvale, CA)
- …computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high ... + 3 years of experience working on PCIe design + Experience interacting with software, system ...Google's services. As a Hardware Engineer , you design and build the systems that are… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and ... Responsibilities:** * Physical Design : Handling the physical design activities and closure of complex sub- system ...Ensuring that the block meets timing requirements of the chip 's subsystem , by optimizing clock tree synthesis, placement,… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of SOC ... clocking. The team collaborates with the front end design team to understand the clocking requirements for the... team to understand the clocking requirements for the chip , interacts with the floor-planning and back end teams… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer ! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU on- chip ... and off- chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Design Engineer ! NVIDIA is seeking best-in-class CPU Design Engineers to design and implement the world's leading CPU's ... design and implementation of high-performance, low power CPU sub- system modules. You will work closely with architects, ...CPU subsystems. + Exposure to Computer Architecture and Digital Systems design . + Highly proficient in logic… more