- SpaceX (Sunnyvale, CA)
- Sr . Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... enabling human life on Mars. SR . SOC/ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON ENGINEERING)...critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior :… more
- Siemens Digital Industries Software (Fremont, CA)
- …& Development **Req ID:** 383049 Company: Siemens Job Title: Sr . Software Engineer - High Level Synthesis Job Reference #: 383049 Job Location: Fremont, ... targeted for FPGAs (https://en.wikipedia.org/wiki/FPGA) and ASICs (https://en.wikipedia.org/wiki/ Application -specific\_integrated\_circuit) . https://eda.sw.siemens.com/en-US/ic/ic-design/high-level- synthesis -and-verification-platform/ Catapult… more
- SpaceX (Sunnyvale, CA)
- Sr . FPGA/ASIC Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. SR . FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...new skills COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- Sr . ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER , DDR IP (SILICON...critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- Qualcomm (Santa Clara, CA)
- …through the full ASIC development process from specification, RTL implementation, verification, synthesis , timing closure, emulation and post silicon bring up. + The ... a moderate amount of influence over key organizational decisions (eg, is consulted by senior leadership to make key decisions). * Tasks do not have defined steps;… more
- Microsoft Corporation (Mountain View, CA)
- …sites within the Microsoft silicon engineering organization. We are looking for a ** Senior Silicon Engineer ** to join our team! **Microsoft's mission is to ... making across UPF (Unified Power Format)/Low Power methodology/architecture, DFT methodology, Synthesis , Place and Route and Extracted Timing model generation in… more
- Microsoft Corporation (Santa Clara, CA)
- The Microsoft Silicon Engineering and Solutions Team is looking to hire a ** Senior Silicon Engineer ** to join our Central Front-End Tools, Flows and Methodology ... VIP Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis , RTL Power Analysis, Physical Design ( PD) Handoff and System on… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... responsible for all aspects of front-end design implementation methodologies ( synthesis , formal-equivalence-checking), flow automation and application support. +… more
- Microsoft Corporation (Mountain View, CA)
- …where everyone can thrive at work and beyond. We are looking for a ** Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis , and System on Chip (SOC) integration on different subsystems.… more
- Microsoft Corporation (Mountain View, CA)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Physical Design Engineer ** to work on leading edge Intellectual Property ... of experience in hardware design. + 4+ years of experience in synthesis , timing constraints and timing closure, front-end design checks, place-and-route and PPA… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …technology. We are excited to welcome highly talented hardware designers and application engineers to join our Cadence North America Field Applications Team. Working ... with IC digital implementation flows and font-end EDA tools including Synthesis , DFT, and Logical Equivalence CheckingPrior experience with Cadence tools such… more
- Microsoft Corporation (Santa Clara, CA)
- …Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer - IO. You will join our front-end silicon team and ... for all employees to positively impact our culture every day. **Responsibilities** As a Senior Silicon Engineer -IO in the Data Processing Unit team you will be… more
- Microsoft Corporation (Santa Clara, CA)
- …(DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Silicon Engineer . You will join our front-end silicon team and ... high performance, low power, scalable and programmable DPU silicon. **Responsibilities** + As a Senior Silicon Engineer in the Data Processing Unit team you will… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for ... 3DIC. + Working with customers in one or more of the following areas: Synthesis , Place and Route, timing and power signoff. + Understanding and proliferating Cadence… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and will be able to collaborate successfully as needed with the digital, analog and application teams. Candidate should be willing to work full time in the San Jose ... of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding… more
- Qualcomm (Santa Clara, CA)
- …the finite-precision models into ASIC hardware using SystemC/C++ for HLS(High-Level Synthesis ) as the primary hardware description language that meet the area ... designs in stand-alone and integrated with the system . Synthesis and gate-level timing tasks related to the designed...of work experience in a role requiring interaction with senior leadership (eg, Director level and above). **Principal Duties… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and implementation of products ... processes, and an understanding of timing closure, clock tree synthesis , power optimization, and physical verification methodologies. Additionally, communication… more
- Siemens Digital Industries Software (Fremont, CA)
- …& Development **Req ID:** 396866 Company: Siemens EDA Job Title: OPC Product Engineer Job Reference #: 396866 Job Location: Wilsonville, OR, Fremont, CA Siemens EDA ... team with a primary focus on development of mask synthesis flows and solutions for patterning processes. The Product... flows and solutions for patterning processes. The Product Engineer role provides an extraordinary opportunity to help define… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, validate, ... of work experience in a role requiring interaction with senior leadership (eg, Director level and above). **Principal Duties...of highly complex process flow from high-level design to synthesis , place and route, timing and power use, and… more