- Meta (Columbus, OH)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation. 20.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Insight Global (St. Paul, MN)
- Job Description We are seeking a highly skilled Sr. Staff/Principal ASIC Design Verification Engineer to lead our verification efforts across complex ... UCIe), AI/ML, complex data processing, and/or processor-based designs. -Familiarity with formal verification techniques and tools. -Knowledge of FPGA prototyping… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The...teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:… more
- Qualcomm (San Diego, CA)
- …such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware ... closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and...as UVM or OVM and exposure to Assertion based Formal Verification + 3+ years of experience… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The...teams towards creating a first-pass silicon success. **Required Skills:** ASIC Design Verification Engineer Responsibilities:… more
- Qualcomm (Santa Clara, CA)
- …products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete ... such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware… more
- Meta (Austin, TX)
- …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Develop functional tests ... verification based on SystemVerilog UVM/OVM based methodologies 14. 7. Functional verification , including SV Assertions, Formal or Emulation 15. 8. EDA tools… more
- Amazon (San Diego, CA)
- …in the validation of FPGAs using test benches, which can be reused for the ASIC implementation . Run formal verification of complex blocks to ensure ... in communication systems - Familiarity with Matlab - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is committed… more
- SpaceX (Irvine, CA)
- …chip and block level front-end implementation from timing constraints development, synthesis, formal verification , power intent generation & validation + Develop ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...various IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification , power intent verification … more
- Google (Mountain View, CA)
- …Engineering, Computer Engineering, or Computer Science. + Experience in different verification techniques and methodologies (eg, formal , GLS, UPF based ... equivalent practical experience. + 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog....or formally verify designs with SVA and industry leading formal tools. + Debug tests with design engineers to… more
- Qualcomm (San Diego, CA)
- …power, high performance ASIC /SoC design flows (micro-architecture, RTL design, verification , synthesis, timing/STA, UPF, CLP, LEC formal verification , ... compute, AI and XR space. An ideal candidate will oversee definition, design, verification , and documentation for ASIC development for a variety of products.… more
- Amazon (Sunnyvale, CA)
- …digital verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more
- L3Harris (Camden, NJ)
- Job Title: Lead ASIC /FPGA VHDL Design Engineer Job Code: 15340 Job Location: Camden, NJ (relocation can be provided for those that qualify) Schedule: 9/80 ... Preferred. + 7+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC /FPGA products. +… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Gate Level and identify power reduction opportunities. 3. Run Formal Verification checks between RTL and Gate… more
- Northrop Grumman (Dulles, VA)
- …are not only part of history, they're making history. We have openings for a **FPGA/ ASIC Engineer ** to join our team of qualified, diverse individuals in the ... as oscilloscopes and logic analyzers. + Generation of Test Benches and support of formal VHDL Verification The Northrop Grumman Tactical Space Division is a… more
- Micron Technology, Inc. (Minneapolis, MN)
- …+ Experience with industry-standard tools related to synthesis, linting, equivalency, and formal verification . + Candidate should be collaborative, curious, and ... this exciting and outstanding opportunity. As a Digital Design Engineer in Micron's ASIC logic design team,...+ Interact with FEOL and BEOL teams from Design Verification , Analog Design, and Modeling to Synthesis and Physical… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems. 10. Experience with Synthesis, Timing Closure and Formal Verification Methodology. 11. Master's or PhD… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 12. Experience with Synthesis, Timing Closure and Formal Verification Methodology 13. Master's or PhD… more