- Microsoft Corporation (Hillsboro, OR)
- …that will manage and optimize the Cloud infrastructure. We are looking for a ** SoC Hardware Validation Engineer ** to join the team. **Microsoft's mission is to ... a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, to firmware, and algorithms.We are seeking an SoC Modeling ASIC Engineer to support C++/Python modeling and software ... and mapping software pipelines to the dedicated hardware accelerators. **Required Skills:** SoC Modeling ASIC Engineer Responsibilities: 1. Analyze the software… more
- SpaceX (Irvine, CA)
- Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...with power intent and upf development for block and soc top. + Familiar with formal verification … more
- NVIDIA (Santa Clara, CA)
- We are looking for SOC Design Engineer ! The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a ... SOC ) group is looking for a top ASIC Engineer with a curiosity about SOC design...integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and… more
- Qualcomm (San Diego, CA)
- …to join a fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs in sub-5nm process nodes for mobile, AI, Compute and ... sound ASIC engineering practices with minimal supervision + Executes the design and verification strategies according to ASICs, SoC , and IP cores specifications… more
- Amazon (San Diego, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We ... STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a SOC /IP Methodology Engineer to help design and architect next generation custom SoC /IP solutions. We are looking for special ... deliver innovative products. Together, we will build the next generation of life changing SoC 's. If you are a motivated individual that understands how SoC … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …place&route and signoff) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing ... technology requirements in the digital , custom and function verification space, coordination of sales strategies and efforts across...in sales and account management or as a Applications Engineer or Design Engineer with proven track… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and ... supports static RTL verification methodologies for RTL Lint and Logical Equivalence. As...limits of technology and performance for GPU, CPU and SoC markets. What you'll be doing: + Evaluate new… more
- Meta (Columbus, OH)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to...at NVIDIA. + Work closely with software, architecture, design, verification , and silicon validation teams. + Train and mentor… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- Microsoft Corporation (Mountain View, CA)
- …servers, clients, and augmented reality. We are looking for a **Principal Design Verification Engineer ** to work on leading edge IP (intellectual property) ... and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components to interface between...of experience in design verification with full verification cycle on complex System on Chip( SoC )… more
- Northrop Grumman (Linthicum, MD)
- …ASIC at block level and SOC level using UVM (Universal Verification Methodology ) and SystemVerilogl. + Development of testbench, tests, verification ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...IP integration and/or development + Experience with a coverage-driven verification methodology from planning through closure +… more
- Capgemini (Santa Clara, CA)
- …*Architect and Create verification environments using System-Verilog and Universal verification methodology -UVM IPs and SoCs with embedded CPUs and analog ... * Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex Microcontroller is required. *… more
- Siemens Digital Industries Software (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and HVL, as well… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...plans based on the Architecture and Micro-architecture. + Develop Verification Methodology , ensuring scalability and portability across… more
- Northrop Grumman (Linthicum, MD)
- …complex ASIC at block level and SOC level using UVM (Universal Verification Methodology ) and SystemVerilog. This task includes but not limited to development ... NGMS, Digital Technologies Group, is seeking a Staff Digital Verification Engineer to support ASIC and FPGA...Advanced Knowledge of UVM and use of a coverage-driven verification methodology + Experience developing test plans,… more