- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Amazon (Cupertino, CA)
- …we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze ... - BS + 4yrs or MS + 3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
- SpaceX (Sunnyvale, CA)
- Principal FPGA/ ASIC Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL FPGA/ ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Science, Engineering, or related field and 1+ year of ASIC design , verification, validation, integration, or related...systems modelling language proficiency is a plus - WIFI Physical layer knowledge is a plus **Principal Duties &… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/ Physical Synthesis using advanced ... in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with...Power, Performance, Area. 14. Knowledge of front-end and back-end ASIC tools. 15. Experience with RTL design … more
- NVIDIA (Santa Clara, CA)
- … Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated Senior ASIC Engineer , Timing to join our...intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,… more
- NVIDIA (Santa Clara, CA)
- …performance designs + Expertise in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication skills + Background in ... We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking...Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our next-generation mobile,… more
- Amazon (Sunnyvale, CA)
- …in Electrical / Communications Engineering - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is committed to ... Estimate power, performance, and area for significant IPs early in design cycle - Execute on design specifications to deliver high quality RTL - Ensure quality… more
- Cisco (San Jose, CA)
- …to physical design signoff activities. What You'll Do You will be part of ASIC physical design Team which is responsible for full Chip physical ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture...from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to integrating such high power devices into complex scalable enterprise grade hardware. The design / verification / physical design of these ASICs pushes ... limits. This particular position requires the individual to be part of ASIC Design effort of the next generation emulation processors Job Requirements: +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In… more
- Qualcomm (Santa Clara, CA)
- …to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL ... Signal Integrity, Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) + Expert in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASIC /IP tapeouts. Knowledge of the IP/SoC ... your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the...You will also be responsible for interfacing with the Physical Design team on STA, timing closure… more
- NVIDIA (Santa Clara, CA)
- …The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build ... We are looking for SOC Design Engineer ! The complexity of the...GPU and Tegra chips and interface, directly with unit-level ASIC , Physical Design , CAD, Package… more
- NVIDIA (Santa Clara, CA)
- …The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build ... Are you looking for a SOC Design Engineer opportunity? If yes, come...GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design , CAD, Package… more