- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for a SOC Design Engineer opportunity? If yes,...complex GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Google (Sunnyvale, CA)
- …data centers affecting millions of Google users. You will join a team working on SoC - level RTL design for data center accelerators. In this role you ... silicon, emulation, FPGA validation and debug, functional verification, physical design , and DFT methodologies. + Experience with SOC.... + Own the planning, creation, and delivery of top - level RTL/deliverables for ASIC and SOC… more
- SpaceX (Sunnyvale, CA)
- …and STA Signoff + Experience with power intent and upf development for block and SOC top + Familiar with formal verification and implementing functional ECOs + ... SOC /ASIC Synthesis & Front-End STA Engineer (Silicon Engineering)... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- Meta (Sunnyvale, CA)
- …and/or C/C++ based verification. 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... of detailed test plans for the different modules and top levels. 3. Implement scalable test benches including checkers,...6. Support hand-off and integration of blocks into larger SOC environments. 7. Develop and drive continuous Design… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …used for system- level characterization, first at block and then eventually at SoC level . The analysis will be carried out to capture system ... as introduction of the active back side. Second, additional high- level tools will be required for design ...for performance, power, area, cost, and temperature (PPACT). On top of EDA enablement, there is also a fundamental… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …Floor planning, layout design and physical verification of active circuits. + Top - level simulations to validate ASIC integration. + Document design ... IC design flow and CAD toolsfor schematic entry, simulation, and layout design , including physical verification and top - level integration. + Solid… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …SOCs. The verification side include pre-silicon RTL verification on block, subsystem and top level . With meticulous attention to details, the individual will ... Digital Design and Verification Engineer will work closely with SoC architects and senior engineers, deploying Cadence technology in demanding customer projects,… more
- Meta (Sunnyvale, CA)
- …verification and UVM methodology. 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... and track detailed test plans for the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test… more
- Actalent (Sunnyvale, CA)
- …+ Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... Description: Run Logic/Physical Synthesis and generate optimized Gate Level Netlist for Timing Area Power. Debug the...PTPX must have. + Experience with RTL Synthesis and design optimization for Power Performance Area. + Experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Palladium and Protium Emulation products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers. This position ... that combine a Virtual Machine running a production OS with the customer's SOC Design running on Candence's Palladium emulation or Protium Prototyping platforms.… more
- Capgemini (Santa Clara, CA)
- … convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verification. - 15 years' experience ... with SoC design (Digital design and development RTL) - Experience with chiplet architecture and partitioning for SiP packages. - Experience with various bus… more
- Amazon (Sunnyvale, CA)
- …Engineering. - 7+ years in semiconductor companies as a Sr. DFT Engineer. - Top level DFT architecture definition experience. - Scan insertion tools and ... in writing verilog/system verilog RTL related to DFT logic design . - Experience in Chip level DFT...level DFT verification methodology and flow. - Perform SOC /IP DFT Gate- level simulations. - Static timing… more
- Cisco (San Jose, CA)
- …of System Verilog and UVM methodology * Experience in verifying complex blocks, clusters and top level for SoC * Can build testbenches from scratch, hands ... Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers...that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through… more
- Meta (Sunnyvale, CA)
- …**Preferred Qualifications:** Preferred Qualifications: 20. 8+ years of experience with system- level design including circuit design , system bring-up, ... complex products to production. 16. Experience in working with external manufacturing and design partners (CM, ODM). 17. Experience with SoC , RF (WiFi/BT),… more
- Fresh Consulting (Sunnyvale, CA)
- …Tcl) - Experience in writing silicon IP reference models using C++. - Understanding of SoC and ASIC design flow. Education: BSCSE or related. FRESH-- - Work on ... Fresh Consulting is a design -led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring… more
- Palo Alto Networks (Santa Clara, CA)
- …skills + Excellent professional presence and confidence working with and advising entry level through top executives + A team player that creatively and ... Work closely with key internal and external stakeholders to design and deliver programs that maximize influence and customer...presentations will be delivered to both Analysts and Executive level staff from a wide variety of industries **Your… more
- Fresh Consulting (Sunnyvale, CA)
- Fresh Consulting is a design -led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring ... together amazing UX designers, sophisticated developers, digital strategists, and top -notch engineers to help companies create fresh experiences that connect humans,… more