• Senior ASIC Timing

    NVIDIA (Westford, MA)
    …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
    NVIDIA (08/01/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Westford, MA)
    …Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization and verification support. The ideal candidate ... + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing design documentation, triaging and debugging functional and… more
    NVIDIA (08/16/24)
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  • FPGA Design Engineer II

    BAE Systems (Burlington, MA)
    …hearing from you! Electronic Combat Solutions Hardware Engineering Group is looking for a Senior FPGA Design Engineer to support FPGA designs through all phases ... Description : BAE Systems is seeking a FPGA Design Engineer II See what you re missing. Our employees...implementation, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing and… more
    BAE Systems (09/06/24)
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