- Qualcomm (Austin, TX)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (Austin, TX)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and...nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical … more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer, you will work with ... + Experience with Synthesis, place and route and signoff timing /power analysis. + Knowledge of high performance and low... design , Circuits, CAD) to solve key physical design problems in CPU … more
- Qualcomm (Austin, TX)
- …with CAD team to ensure proper and efficient model generation + Interacting with Physical Design team resolve memory PPA challenges + Depending on skill set, ... to build products to change the world. As a CPU SRAM Design Engineer, you will ...designs + Experience with all memory analysis steps including design entry, functional verification, layout guidance, simulation, timing… more
- Qualcomm (Austin, TX)
- …synthesis, place & route and tape out flows. Roles and Responsibilities + Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP ... and physical design teams to design , floorplan and integrate the CPU designs...+ Proficiency in synthesis, place and route, and signoff timing /power analysis. + Expertise in block-level implementation as well… more
- Qualcomm (Austin, TX)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more