- Marvell Technology, Inc. (Santa Clara, CA)
- …circuit design, testing, and timing analysis . Strong understanding of standard RTL to GDS flows and methodology . Strong scripting skills in languages ... you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a… more
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- Cisco (San Jose, CA)
- Senior DFx/ RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis +… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy constraints checks. We're looking… more
- NVIDIA (Santa Clara, CA)
- …field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology , or constraint development. + Strong expertise in asynchronous ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has...Be Doing: As a key member of our DFX Methodology Team, you will play a critical role in ... + 5+ years of hands-on experience in SoC architecture, RTL design, and verification. + Strong proficiency in micro-architecture...is a plus.) + Deep expertise in DFT design, methodology , and implementation. + Familiarity with related domains such… more
- Microsoft Corporation (Mountain View, CA)
- …(PD) domain. + Facilitate coordination across cross-functional teams, including DFT, RTL /Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power & ... will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Physical Design Engineer** to join the team. **Responsibilities** + Accountable for… more
- Microsoft Corporation (Santa Clara, CA)
- …(DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer. You will join our front-end silicon team and be responsible ... cutting-edge, high performance, low power, scalable and programmable DPU silicon. As a Senior Silicon Engineer in the Data Processing Unit team you will be… more
- Google (Mountain View, CA)
- …CPU architecture and CPU blocks. + Experience in performance modeling, analysis , correlation, and workload characterization. + Experience with C/C++ and scripting ... hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Senior CPU Architecture and Performance Architect, you will be the key… more
- NVIDIA (Santa Clara, CA)
- …chip leads, and customers on SoC IP design, timing closure, power analysis , methodology alignment, and program execution, ensuring success from pre-silicon ... lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What...experience). + 10+ years of relevant work experience in RTL development passionate about CPU, GPU, and HPC architectures.… more
- NVIDIA (Santa Clara, CA)
- …Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks + Collaboration with physical design to… more
- Cisco (San Jose, CA)
- …and power requirements. + Contribute to full chip integration and timing methodology / analysis . + Develop and analyze functional coverage. + Help define, ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San...evolve, and support our design methodology . + Collaborate with the verification team to address… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Engineering, or related field + 12+ years of design/EDA experience ( methodology , flow, implementation, RTL2 GDS) + Proven experience in leading, managing, ... knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with IC digital implementation flows… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We ... Key job responsibilities * Includes definition and development of signoff methodology and corresponding implementation solution * Flow for STA, Crosstalk Delay… more
