- Broadcom (Irvine, CA)
- …design background is preferred & the candidate should have a strong scripting/ automation experience using Python / Perl Must have strong communication and ... documentation skills. Must be a self-starter and a strong team player. Candidates will primarily be responsible for working on automating design flows, supporting synthesis deliverables & STA. Apart from this, the candidate is also expected to handle minimal… more
- Meta (Sunnyvale, CA)
- **Summary:** META is hiring ASIC Silicon Infrastructure Engineer within our Reality Lab ASIC organization. We are looking for individuals with experience in ... EDA flow, CAD/ automation and ASIC infrastructure to build efficient...(design flow steps, sanity checks, regression, etc) **Required Skills:** ASIC Silicon Infrastructure Engineer Responsibilities: 1. Work… more
- Qualcomm (San Diego, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration , or related work experience. OR ... Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration , or related work experience. OR PhD… more
- Qualcomm (San Diego, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration , or related work experience. OR ... low-power digital design - Experience in creating tools and automation flows (in Python, Perl, or C) for improving...Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration , or related… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration , or related work experience. OR ... Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration , or related work experience. OR PhD… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration , or related work experience. OR ... Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration , or related work experience. OR PhD… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC ... **Summary:** Meta is hiring ASIC Methodology Engineers within our Infrastructure organization to...a timing signoff perspective. 4. Develop robust timing signoff automation and test structures to ensure Meta's timing methodology… more
- Meta (Sunnyvale, CA)
- …to joining Meta. 14. 5+ Years of experience as a Front End Synthesis & Integration Engineer 15. Experience with RTL Synthesis and design optimization for Power, ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Meta (Sunnyvale, CA)
- …Minimum Qualifications: 10. 10+ Years of experience as a Front End Synthesis & Integration Engineer 11. Experience with RTL Synthesis and design optimization for ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... the boundaries of what's possible! Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Gate Level Netlist for Timing, Area, Power. 6. Developing Automation scripts and Methodology for all FE-tools including (… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
- NVIDIA (Santa Clara, CA)
- …outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering ... Improve the speed, flexibility, and extensibility of the High-Speed IO front end integration , build, and verification flows + Apply best in class internal and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... architecture, intent, and implementation of the various IPs. + Enable system level integration by working with partner teams for test development & debug and… more
- Google (San Diego, CA)
- …+ 5 years of technical experience in silicon timing closure and chip integration . + Experience with STA signoff constraint authoring for full-chip level, tapeout ... signoff requirements, checklists, and associated automation . + Experience in one or more static timing...silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis.… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Teledyne (Goleta, CA)
- …and high reliability. These markets include aerospace and defense, factory automation , air and water quality environmental monitoring, electronics design and ... early system trades as well as support for camera integration and production. You will be tasked take the...engineers on an image sensor are small, so each engineer is responsible for the design trades and implementation… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** **Design Automation Engineer ** This position is part of a team tasked with ... of use is critical. **Responsibilities:** Develop and support design automation flows for ASIC products and associated...arising from LVS, ERC and DRC errors + Design automation flow support and development + Integration … more
- Meta (Fremont, CA)
- **Summary:** The Systems Integration Engineer (SIE) is responsible for the successful Integration of new hardware platforms & new infrastructure technologies ... the role for you. This position is full-time. **Required Skills:** Systems Integration Engineer Responsibilities: 1. Lead new product introduction and associated… more