• ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/ IP /System on Chip ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
    Meta (09/04/25)
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  • ASIC Engineer , Design

    Meta (Sacramento, CA)
    …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
    Meta (08/29/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
    Meta (08/01/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...2. Micro-architecture development 3. Soft and hard IP identification, selection and integration. Collaboration with verification and… more
    Meta (08/01/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Verilog, System Verilog and HLS 4. Soft and hard IP identification, selection and integration 5. Collaboration with verification… more
    Meta (08/01/25)
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  • ASIC Engineer , Network…

    Meta (Sunnyvale, CA)
    …silicon success. **Required Skills:** ASIC Engineer , Network Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
    Meta (09/30/25)
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  • ASIC Engineer , Physical…

    Meta (Sunnyvale, CA)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... 3. Deliver physical design of an end-to-end IP or integration of ASIC /SoC design...to $203,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an… more
    Meta (08/29/25)
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  • ASIC Engineer , IP

    Google (Mountain View, CA)
    ASIC Engineer , IP Design , Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and ... with an emphasis on computer architecture. + 10 years of industry experience with IP design . + Experience with methodologies for low power estimation, timing… more
    Google (10/03/25)
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  • Sr. ASIC Design Engineer

    Amazon (Cupertino, CA)
    design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...innovate, explore new solutions, and contribute to the company's intellectual property through patents About the team… more
    Amazon (09/13/25)
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  • Senior ASIC Design Engineer

    Arrow Electronics (San Jose, CA)
    **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... prototyping methodology. + **Option to engage in block-level RTL design or block or top-level IP integration.**...by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree… more
    Arrow Electronics (09/10/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... management solutions. + Define micro-architecture and specifications of digital IP blocks to improve the power and performance of...+ Strong familiarity and experience with all stages of ASIC design flow including front end … more
    NVIDIA (08/27/25)
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  • ASIC Design Verification…

    Google (Mountain View, CA)
    ASIC Design Verification Engineer , Devices and Services _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving ... unparalleled performance, efficiency, and integration. As an Application-Specific Integrated Circuit ( ASIC ) Design Verification Engineer , you will be… more
    Google (10/04/25)
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  • Staff ASIC Design Verification…

    Google (Mountain View, CA)
    Staff ASIC Design Verification Engineer , Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes ... scripting languages, Software (SW) development frameworks and their impact on Design Verification (DV). + Experience creating and using verification components and… more
    Google (10/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... and DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all… more
    NVIDIA (07/29/25)
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  • ASIC Modem Design Engineer

    Amazon (San Diego, CA)
    …communities around the world. Come work at Amazon! We're hiring a Modem Design Engineer within a high performance ASIC design team. This team is using ... industry leading methodologies to develop proprietary IP 's. The Role: Be part of Project Kuiper's sub-team...and system engineers to drive hardware micro-architecture and datapath design . - Able to interpret reference models in MATLAB.… more
    Amazon (09/13/25)
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  • Sr. ASIC Design Engineer

    Amazon (Hawthorne, CA)
    …specifications suitable for being implemented by junior engineers -Evaluate 3rd party IP blocks -Estimate power, performance, and area for significant IPs early in ... design cycle -Execute on design specifications to deliver high quality RTL -Ensure quality by running and tracking results of front-end tools including:… more
    Amazon (10/08/25)
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  • ASIC and/or FPGA Design

    The Boeing Company (Huntington Beach, CA)
    …through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate DSP IP from Boeing's algorithm team and ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers...Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products… more
    The Boeing Company (10/04/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... analysis, physical verification, ECO and sign-off - Develop physical design methodologies - Evaluate 3rd party IP ...MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in… more
    Amazon (09/02/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... analysis, physical verification, ECO and sign-off - Develop physical design methodologies - Evaluate 3rd party IP ...power, area analysis and trade-offs - Experience with modern ASIC /FPGA design and verification tools - Experience… more
    Amazon (10/02/25)
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  • Senior Applications Engineer - DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops industry leading IPs that enable customers… more
    Cadence Design Systems, Inc. (10/04/25)
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