- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...Qualifications:** Minimum Qualifications: 8. 5+ years of experience in static verification tools 9. Experience with Lint, Clock Domain… more
- Google (Mountain View, CA)
- …with high complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + ... and associated automation. + Experience in one or more static timing tools (eg, PrimeTime, Tempus). Preferred qualifications: +...and their tradeoffs. + Drive clock tree planning and implementation for SoCs to achieve best energy, performance and… more
- The Boeing Company (Huntington Beach, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... of ASIC /FPGA design or verification experience + Experience with ASIC /FPGA architectural definition, and detailed design implementation and functional… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation . What we need to see: + Hold a BS in Electrical or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
- NVIDIA (Santa Clara, CA)
- …generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
- Amazon (Sunnyvale, CA)
- …high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA tools and flows ... of the design automation and methodology team and deliver digital design implementation flows to design teams using various silicon processes - Develop, regress,… more
- Google (Sunnyvale, CA)
- …AI/ML-driven systems. In this role, you will work on the physical implementation of Application-specific integrated circuits ( ASIC ) using advanced technology ... and timing signoff execution. + Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction… more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints ... for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile,… more
- Broadcom (San Jose, CA)
- …working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with the ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...physical implementation team from initial floor planning to final timing… more
- Qualcomm (San Diego, CA)
- …> ASICS Engineering **General Summary:** We are looking for a physical design engineer to join our design team in San Diego California. Successful candidate will ... be part of design group responsible to deliver IP implementation like high-speed DDR, USB, PCI, PLL and mixed...Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.… more
- Meta (Sunnyvale, CA)
- … Engineer Responsibilities: 1. Develop and own physical design implementation of multi-hierarchy low-power ML Hardware design including physical-aware logic ... and back-end hardware designers to drive the Physical design implementation of ML compute blocks in advanced technology nodes...synthesis, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification… more
- SanDisk (Irvine, CA)
- …the Firmware on SoC platforms, as well as bringing up of FPGA and ASIC . + Contribute to the Security Development Lifecycle of the Firmware by supporting its ... development at different stages, including design, threat analysis, implementation , validation, vulnerability testing, certification, and audit. **Qualifications** **REQUIRED:**… more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more