- Qualcomm (San Diego, CA)
- …Inc. **Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing ... and Tempus. + You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...for STA timing sign off. + A timing Engineer should be able to understand… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ... **Summary:** Meta is hiring ASIC Methodology Engineers within our Infrastructure... signoff automation and test structures to ensure Meta's timing methodology is A0-production ready. 5. Drive… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... with multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU,… more
- Google (Mountain View, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Experience in extraction of design ... equivalent practical experience. + 5 years of technical experience in silicon timing closure and chip integration. + Experience with STA signoff constraint authoring… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power. 2. Debug the timing /area/congestion… more
- Qualcomm (San Diego, CA)
- … ASIC /SoC design flows (micro-architecture, RTL design, verification, synthesis, timing /STA, UPF, CLP, LEC formal verification, DFT, physical design.) + Hands-on ... company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and...performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in sub-4nm process for… more
- Qualcomm (San Diego, CA)
- …Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. ... such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power… more
- Palo Alto Networks (Santa Clara, CA)
- …create an environment where we all win with precision. **Your Career** Join our ASIC team and help deliver the digital logic that powers our next-generation firewall ... platforms. As a Senior Principal Engineer , you will take end-to-end ownership of complex modules...members. This role requires a deep technical background in ASIC design for networking applications and the ability to… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...Timing , Area, Power. 6. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,). 7.… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines ... synthesis, design for test, floorplanning, place and route, clock methodology , power planning and analysis, timing closure,...+ Requires a minimum of 8 years of related ASIC implementation experience. + BS degree in Electrical Engineering… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... doing: + As a key member of the DFX methodology team, you will be responsible for the architecture,...architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams + Work on generating test… more
- Google (Mountain View, CA)
- …language like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology . Preferred qualifications: + Master's degree or PhD in ... with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL quality checks (eg,… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing ... multiple projects covering CPUs and GPUs + Collaborate with methodology leads, and timing engineers to refine...3+ years' experience in ASIC Design and Timing . + Knowledge of device physics, STA methodology… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... next-generation GPUs and SoCs. In this role, you'll develop methodology and flows to validate timing constraints...Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing . + Expertise in… more