• Wrap Expanded Learning Program Leaders (Recreation…

    City of Long Beach (Long Beach, CA)
    …LEARNING PROGRAM LEADERS (RECREATION LEADER SPECIALIST VII-N/ C ) Print (https://www.governmentjobs.com/careers/longbeach/jobs/newprint/4544859) Apply  WRAP EXPANDED ... LEARNING PROGRAM LEADERS (RECREATION LEADER SPECIALIST VII-N/ C ) Salary $20.87 Hourly Location City of Long Beach, CA Job Type Unclassified - Part-Time, Seasonal Job… more
    City of Long Beach (04/17/25)
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  • Clinical Nurse (RN), ICU Neurosciences & Medicine…

    Stanford Health Care (Palo Alto, CA)
    …career. Magnet Designated The American Nurses Credentialing Center (ANCC) Magnet Model provides a framework for clinical, operational, and leadership practice, ... ongoing pursuit toward nursing excellence. PPM The SHC Professional Practice Model (PPM) illustrates how nurses support the organization's mission, vision, and… more
    Stanford Health Care (05/30/25)
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  • Applied Research Scientist, Systems ML - SW/HW…

    Meta (Sunnyvale, CA)
    …to improve Meta's products and experiences. 2. Develop state-of-the art model compression and scalability techniques using Numerics, pruning, distillation etc. 3. ... one or more of the following machine learning domains: Model compression, hardware-aware model optimizations, hardware accelerators...infrastructure , AI algorithms or AI hardware acceleration in C / C ++ or Python. 12. Must obtain work… more
    Meta (04/04/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …practical experience. 8. 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C / C ++ based verification. 9. Track record of 'first-pass ... Design verification of Data-center applications like Video, AI/ML and Networking designs. 17 . Experience with verification of ARM/RISC-V based sub-systems or… more
    Meta (05/06/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …practical experience. 9. 10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C / C ++ based verification. 10. 10+ years experience in ... closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation,… more
    Meta (04/18/25)
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  • Clinical Nurse (RN), Apheresis (On-Call) - 10HR…

    Stanford Health Care (Palo Alto, CA)
    …growth and work-life balance, while honoring its commitment to delivering evidence- based and patient-centered care. ANCC Magnet Designation: The American Nurses ... Credentialing Center (ANCC) Magnet Model provides a framework for clinical, operational, and leadership...who provides hands-on care to patients, practicing in an evidence- based manner, within the Scope of Practice of the… more
    Stanford Health Care (05/15/25)
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  • Software Engineer, Machine Learning

    Meta (San Francisco, CA)
    …on Cold Start Users Recommendations, including techniques such as model debiasing, signal development, embedding development, responsiveness, and recommendation ... state-of-the-art deep learning technologies, particularly in applying causal inference, model debiasing to enhance model accuracy and...Spark and Hadoop 14. 7.- Developing and debugging in C , C ++, C # and Java… more
    Meta (06/03/25)
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  • Partner Engineer, PyTorch

    Meta (Menlo Park, CA)
    …Speech, Conversational AI,AI-Infrastructure, Fine-tuning and optimizations of PyTorch models. 17 . Software development experience in languages like Python, Java, Go, ... Rust, C / C ++. (at least one) 18. Experience with...partners 27. Data science background and experience manipulating/transforming data, model selection, model training, model more
    Meta (06/03/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …prior to joining Meta. 8. 3+ years of hands-on experience in Verilog, SystemVerilog, C / C ++ based verification and UVM methodology. 9. 3+ years experience ... the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. 4.… more
    Meta (05/14/25)
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  • Design Verification Engineer

    Meta (San Diego, CA)
    …cycle industry experience. 9. 5+ years of hands-on experience in Verilog, SystemVerilog, C / C ++ based verification and UVM methodology. 10. 5+ years ... the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. 4.… more
    Meta (05/07/25)
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  • Senior Electric Utility Engineer

    Silicon Valley Power (Santa Clara, CA)
    …+ The first position will perform and maintain the distribution system model , participate in integrated SVP system planning with the transmission planning team ... Weekly paid leave for absences due to non-work related injuries/illnesses. Benefit is based on past earnings. Refer to edd.ca.gov for more information **Paid Family… more
    Silicon Valley Power (04/10/25)
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  • Postdoctoral Researcher, Monetization (PhD)

    Meta (Sunnyvale, CA)
    …Monetization, including but not limited to, ranking, retrieval, supply, model architecture, representation learning, optimization, and generally a deep understanding ... such as Pytorch or Tensorflow. 9. Experience with Python, C ++, C , Java, or other related languages....related languages. 10. Experience with research and building systems based on Machine Learning and/or Deep Learning methods. 11.… more
    Meta (06/03/25)
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  • QA Engineering Lead (AI)

    Meta (Menlo Park, CA)
    …assurance and test engineering experience. 12. 1+ years of experience in AI model testing/evaluations and setting model quality standards. 13. Experience in ... Python, PHP, Java, C / C ++ or equivalent coding language. 14. Experience...adapt effectively in a fast moving product development cycle. 17 . Hands-on experience with test planning, test designing and… more
    Meta (05/14/25)
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  • Deputy Sheriff Cadet

    Stanford University (Stanford, CA)
    …920 hours of academic classes, hands-on training and physical conditioning. Knowledge- based training includes, but is not limited to: Criminal Law, Patrol ... possess the followingqualifications and/or skills: **Leadership** * Promote and model the department's Core Values, ROOTS philosophies and department/university… more
    Stanford University (05/08/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …prior to joining Meta. 7. 3+ years hands-on experience in SystemVerilog/UVM methodology or C / C ++ based verification 8. Track record of 'first-pass success' ... Design team 5. Collaborate with cross-functional teams like Design, Model , Emulation and Silicon validation teams towards ensuring the...Git or SVN 16. Experience with verification of ARM/RISC-V based sub-systems or SoCs 17 . Experience with… more
    Meta (03/08/25)
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  • Design Verification Engineer - Machine Learning…

    Meta (Sunnyvale, CA)
    …practical experience. 9. 10+ years of hands-on experience in SystemVerilog/UVM methodology and C / C ++ based verification. 10. 10+ years of experience in ... models, assertions in System Verilog. 4. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.… more
    Meta (05/17/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …core and NOC subsystems 15. 4. SystemVerilog/UVM methodology or C / C ++ based verification 16. 5. ASIC development cycles 17 . 6. IP/sub-system or SoC ... test benches to enable IP/sub-system/SoC level verification. 5. Develop functional tests based on verification test plan. 6. Drive Design Verification to closure … more
    Meta (06/03/25)
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  • Plumber/Steamfitter

    Stanford University (Stanford, CA)
    …the terms and conditions of employment. **Anticipated Shift:** The anticipated shift is based on the operational needs and can change at any time with notice. ... providing housing for over 13,000 students and dependents, serving meals at 17 dining halls, 12 retail locations, and operating athletic concessions and conference… more
    Stanford University (06/02/25)
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  • Design Verification Engineer (University Grad)

    Meta (Sunnyvale, CA)
    …Meta 8. Experience with ASIC development cycle. 9. Experience in Verilog, SystemVerilog, C / C ++ based verification and UVM methodology. 10. Experience in ... the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. 4.… more
    Meta (05/10/25)
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  • Area Director, Delivery

    Meta (Menlo Park, CA)
    …contractor and telecom partners. These roles navigate complex commercial contractual and performance- based issues at the corporate level of the largest data center ... builders in the US, interacting with VP and C suites within those builders to secure and fully...evolves our supply chain to best meet our OKRs. 17 . Proactively monitor project delivery updates, adherence to KPI's… more
    Meta (06/03/25)
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