- Google (Mountain View, CA)
- …embedded SRAM design (cell and macro) and characterization. + Experience in CMOS technology and device characterization, process integration and SPICE ... + Experience in product-level testing in Static Random Access Memory (SRAM) including yield and parametric evaluation. + Excellent...(PDPPA) team to evaluate PPA accounting both logic and memory at IP level. + Work with the IP… more
- Broadcom (Irvine, CA)
- …already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** Memory Circuit Design Engineer ** We are looking for energetic and ... Central Engineering Group and be part of an elite memory team responsible for the development of memory...types such as SRAM, RF, ROM and familiarity with CMOS digital circuits + Good understanding of transistor level… more
- Micron Technology, Inc. (Folsom, CA)
- …scripting language is highly encouraged. + Good understanding of Process Technology and device physics of advanced CMOS device architecture (FinFET and ... **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of...are seeking a motivated and experienced Si Foundry Interface Engineer to focus on the reliability assessment of new… more
- Micron Technology, Inc. (Folsom, CA)
- …Computer Engineering, or related field. Position requires education or experience in: 1. Device physics, CMOS devices, analog and digital circuit design; 2. ... for** **_all_** **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer - someone who is excited to join a rapidly growing team of creative circuit design ... you'll be doing: + Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces + Solve challenges of circuit designs...+ Solve challenges of circuit designs in the latest CMOS FinFET processes + Take designs through productization and… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... 3+ years' experience in ASIC Design and Timing. + Knowledge of device physics, STA methodology. + Good understanding of mathematics/physics fundamentals of… more