- Capgemini (San Francisco, CA)
- …_ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification ( DV ) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** ... **Job description:** Analog/Mixed-Signal Design Verification **Key responsibilities:** + Extract...Develop timing model for the circuit working with layout engineer . + This role will provide the ability to… more
- Cisco (San Jose, CA)
- …and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as ... ASIC in deployment-mode applications * You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the… more
- Amazon (San Diego, CA)
- …technologies. In this role you will: . Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models . ... be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness ....blocks to ensure functional correctness . Work with the design and communication systems team and participate in system… more
- Micron Technology, Inc. (San Jose, CA)
- …models (LLMs) for the purpose of automated Silicon design and Design Verification ( DV ). The engineer is expected to build LLM based EDA workflows ... which assists the Design Engineers in building the next Micron product at...LLMs for the purpose of automated corner case uncovering, design optimization and spec-to- design translation. + Develop… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins Champion the customer needs ... Experience in writing scripts (Perl, Python or Tcl) Strong software, HDL design and verification skills Experience with SystemVerilog, VHDL, Verilog,… more
- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Design Verification Lead, you will lead a team of ASIC design ... a team defining the processes, methods and tools for design verification of large complex IP blocks...+ 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of… more
- BAE Systems (San Diego, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Design Verification Engineer - FPGA - (Sign-on Bonus)** **112648BR** ... career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect,...your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will ... towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1....7. Experience in verifying a IP block using standard DV based techniques. 8. Experience in EDA tools and… more
- Qualcomm (Santa Clara, CA)
- …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... flow and methodology. Involve in developing automation to improve verification efficiency. **Qualifications:** + DV experience using uvm/assertion based… more
- BAE Systems (San Diego, CA)
- …Other incentives may be available based on position level and/or job specifics. **Senior Design Verification Engineer - FPGA** **110464BR** EEO Career Site ... advancing your career. BAE is looking for experienced FPGA Design Verification Engineers who can develop and...evolution of our processes and methodologies. + Enhance your DV skills as well as your knowledge of Electronic… more
- Amazon (Sunnyvale, CA)
- …to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to ... Enhance your leadership skills while contributing to a dynamic DV team * Create reusable Verification IP...verification simulation solutions. The FPGA verification engineer will work with FPGA design and… more
- Cisco (San Jose, CA)
- …customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation ... with outstanding talent and vast ASIC development expertise in design , DV , DFT, physical design ,...* Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and… more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects ... Verification Plans and Testbenches for your functional domain. + Execute Verification Plans, including Design Bring-up, DV environment Bring-up,… more
- Cisco (San Jose, CA)
- …of the most complex ASICs being developed in the industry. Your Impact As ASIC Verification Engineer in The Core Hardware Business Unit, you will be engaged the ... infrastructure for block, cluster and top level environments. *Maintaining existing DV environments and enhancing them *Ensuring complete verification coverage… more
- Amazon (Cupertino, CA)
- …instances, and we invite you to build them with us! As an Architecture Verification Engineer , you will be responsible for ensuring the functionality and ... behaviors, among others. Key job responsibilities As an Architecture Verification Engineer you will: * Gain a...of SoC architecture and micro-architecture * Work with architecture, design , DV and SW teams to verify… more
- Qualcomm (San Diego, CA)
- … verification tests to identify and resolve design issues. In this role of Design Verification Engineer , you will be using advanced state of the art ... connected future for all. We are looking for ASIC Design Verification Engineers with strong CPU, ASIC...setting benchmarks in the whole industry. As an SOC Verification and Methodology Engineer , you will be… more
- Qualcomm (San Diego, CA)
- … verification tests to identify and resolve design issues. In this role of Design Verification Engineer , you will be using advanced state of the art ... where you come in. We are looking for ASIC Design Verification Engineers with strong CPU, ASIC...setting benchmarks in the whole industry. As an SOC Verification and Methodology Engineer , you will be… more
- Cisco (San Jose, CA)
- …with focus on reuse. * Defining new DV methodologies. * End-to-end verification of one or more design blocks simultaneously while helping the full ... products. Your Impact: You are a hard-working, motivated ASIC Verification Engineer who will be joining our... of very complex ASICs. You will have a Design Verification background, in-depth experience in System… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High ... 5+ years of relevant industry experience + Exposure to computer architecture, ASIC design , and verification methodology is required + Experience with … more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior System Verification Engineer to join our Emulation division. We are a worldwide recognized division noted for groundbreaking ... and GPU Coherency + We have continual collaboration with Design , DV , Power, Silicon Validation, Performance, and...Be familiar with hierarchical design approach, top-down design , SoC and system level verification . +… more