• IC Packaging Principal Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Cadence tool set in the context of multiple flows including IC Packaging , high speed design, signal integrity and electrical constraints definition. Design ... experience and industry knowledge of current IC Packaging Design and manufacturing processes is required. Knowledge of...IC Package Design is required. + In-depth knowledge of EDA industry, Signal Integrity, Power Integrity is a plus.… more
    Cadence Design Systems, Inc. (05/23/25)
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  • Staff R&D Engineer Adv Tech Dev

    Broadcom (San Jose, CA)
    …field. **Key Qualifications** + Broad knowledge of advanced silicon and packaging process technologies + Working knowledge of the Advanced Semiconductor Technology ... experience is a plus + Working knowledge of 2.5D packaging technology and 3D stacked IC + Knowledge and...3D stacked IC + Knowledge and use of various EDA offerings from major EDA suppliers in… more
    Broadcom (04/11/25)
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  • Hardware Miniaturization Design Electrical…

    Meta (Sunnyvale, CA)
    **Summary:** Join Meta Reality Labs as a Hardware Miniaturization Design Electrical Engineer and play a pivotal role in shaping the future of the Wearables Product ... Line. As an experienced engineer with a proven track record of collaborating with...working on complex/miniaturized board designs (PCB/FPC/RFPC). 9. Proficiency in EDA tools(schematic capture) and some layout experience. 10. Knowledge… more
    Meta (03/15/25)
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  • R&D Engineer IC Design

    Broadcom (San Jose, CA)
    …advanced packaging design, including CoWoS, 2.5D/3D + Proficiency with EDA tools such as Cadence (Innovus, Integrity), Synopsys (3DIC compiler), Mentor Graphics ... part of your job you will be interacting with packaging , signal integrity and foundries to meet the... , signal integrity and foundries to meet the packaging , SI and physical requirements of the interposers. Experience… more
    Broadcom (05/24/25)
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  • Sr. IC Layout Engineer (Starlink)

    SpaceX (Sunnyvale, CA)
    …includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations + Accurately estimate the schedule ... Sr. IC Layout Engineer (Starlink) Sunnyvale, CA Apply SpaceX was founded...and sharing GDS with the foundry) + Work with EDA suppliers to trial new tools and features +… more
    SpaceX (04/15/25)
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  • Photonic Integrated Circuit (PIC) Test…

    The Boeing Company (Huntington Beach, CA)
    …currently looking for a **Photonic Integrated Circuit (PIC) Test and Characterization Engineer (Associate or Mid-Level)** to join the team based in **Huntington ... development flow in-house including architecture definition, design, layout, verification, packaging , and testing. RPMM owns numerous projects funded by internal… more
    The Boeing Company (05/25/25)
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  • Hardware Engineer , Senior

    Qualcomm (San Diego, CA)
    …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems, bring-up ... yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging , test systems, FPGA, and/or DSP systems that launch cutting-edge,… more
    Qualcomm (06/03/25)
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  • Sr Principal Software Engineer (Boston)

    Cadence Design Systems, Inc. (San Jose, CA)
    …impact on the world of technology. We are looking for a talented software engineer to help design and develop some of the most complex Electronic Design Automation ... ( EDA ) software in the electronics world. Our software is...and develop advanced automated design flows for 3D-IC, IC Packaging and PCB applications* Design and develop cutting-edge placement… more
    Cadence Design Systems, Inc. (04/17/25)
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  • GPU Physical Design Engineer

    Qualcomm (San Diego, CA)
    …PPA + Engaging in cross-functional collaboration with verification, timing, power, and packaging teams to ensure holistic design convergence + Partnering with EDA ... tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency + Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets **The… more
    Qualcomm (05/28/25)
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