- Qualcomm (Santa Clara, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Broadcom (San Jose, CA)
- … constraint development for hierarchical designs. + Knowledge of clock tree planning and implementation for SoCs. + Experience with timing ECO creation and final ... timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg,...Desired Qualifications: + Working with Genus tools (Cadence) for design synthesis including DFT flow, + Review timing… more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA / Timing Engineer/Level I: $120,000.00 - $145,000.00/per year ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...Physical Design STA / Timing Engineer/Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Qualcomm (Folsom, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ). 7. Work closely with the Design ...them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing … more
- Google (San Diego, CA)
- …silicon timing closure and chip integration. + Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, ... in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing ...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA… more
- NVIDIA (Santa Clara, CA)
- …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design...them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 9. Work closely with the Design...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Amazon (Sunnyvale, CA)
- …to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC ... equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with...Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical design .… more
- Meta (Sunnyvale, CA)
- …to develop reset groups and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level ... online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization techniques… more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- Google (Sunnyvale, CA)
- … design flows, and methodologies including synthesis, place and route, Static Timing Analysis ( STA ), formal verification, Change Data Capture (CDC), and power ... at Google (https://careers.google.com/benefits/) . + Perform full chip clock planning. Create timing constraints and own the physical implementation of clock… more
- Broadcom (San Jose, CA)
- …with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency ... ASICs. Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million gates complexity).… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation +...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Google (Sunnyvale, CA)
- …related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the ... of silicon-based ICs and chips. + Experience in logic synthesis, PnR, timing closure, and static timing analysis. Preferred qualifications: + Master's… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …our communities, and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the next generation SoCs. ... This person will also be responsible for the implementation & verification including Scan, PMBIST, JTAG and other...constraints as well as perform RTL and gate level (no- timing and timing ) simulations to verify DFT… more
- Qualcomm (San Diego, CA)
- …+ Experience in static timing analysis, constraints and other physical implementation aspects + Familiar with digital flow design and industry standard ... tools used for RTL to GDS implementation + Good technical writing and communication skills in...debug across multi-mode, multi-voltage domain designs using industry standard timing tools + STA setup, convergence, reviews… more
- Qualcomm (San Diego, CA)
- …entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design , verification, synthesis, timing / STA , UPF, CLP, LEC formal ... using PowerArtist and PrimeTime PX (PTPX) and work with cross-functional teams - design , implementation , and physical design teams - to optimize power. +… more