- Qualcomm (San Diego, CA)
- … team to complete the IP design implementation. + Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ... functional safety feature in automotive SoC product. + Create/Enhance low power methodologies covering entire design...cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design… more
- Qualcomm (Santa Clara, CA)
- …ARM IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, … more
- Qualcomm (San Diego, CA)
- …of next Generation, high performance, low power Memory Subsystem RTL Design , flows and methodology for high performance ASICs in sub-4nm process for ... low power designs. + Strong knowledge in the entire low power , high performance ASIC/SoC design flows (micro-architecture, RTL design ,… more
- Amazon (Cupertino, CA)
- …multiple vendor solutions and driving tool decisions. - Experience in high-performance, low - power physical design , and implementation techniques with ... today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to support… more
- Qualcomm (San Diego, CA)
- … analysis concepts and on-hands experience with PTPX etc. ⦁ Sound conceptual understanding of low power design techniques like voltage/ power islands, ... and validate new flows and methodologies ⦁ Work on design power profiling and electromigration analysis ⦁...in languages such as Python, TCL, Perl ⦁ Strong methodology development background. Ability to drive solutions by creating… more
- NVIDIA (Santa Clara, CA)
- … Engineering + Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes + Strong understanding of physical ... with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design ,… more
- Qualcomm (San Diego, CA)
- …issues wrt constraints validation, verification, STA, Physical design , etc. + Knowledge of low power flow ( power gating, multi-Vt flow, power supply ... to high frequency design convergence for physical design with PPA targets and PDN methodology ....**Principal Duties and responsibilities:** + Complete ownership on Conformal Low Power and Formal Verification signoff for… more
- Qualcomm (San Diego, CA)
- …the rare opportunity to have real impact in shaping 5G product lines ranging from low power Snapdragon chips to the growing field of Machine Learning (AI/ML) and ... + Experience with pre-silicon emulation platform-based verification + Knowledge of Power design , architecture, and verification requirements + Displays a… more
- Qualcomm (San Diego, CA)
- …the rare opportunity to have real impact in shaping 5G product lines ranging from low power Snapdragon chips to the growing field of Machine Learning (AI/ML) and ... in the whole industry. As an SOC Verification and Methodology Engineer, you will be responsible for ensuring the...AMBA Bus, DDR, GPU, Multimedia etc. + Knowledge of Power design , architecture, and verification requirements +… more
- Qualcomm (San Diego, CA)
- …+ **Required Skills:** + Understanding of SoC Power Delivery Network architectures, Low Power Design Techniques for different market segment products ... IPs on emulation and post-silicon platforms. + Collaborate with IP/ Design Teams and power architects to define...+ Strong familiarity with Static Timing Analysis and Physical Design tools & methodology . + Solid understanding… more
- NVIDIA (Santa Clara, CA)
- …fields. + Strong understanding of concepts of energy consumption, estimation, data movement and low power design . + Familiarity with Verilog and ASIC ... networking chips requires the team to provide architecture, micro-architecture, RTL Design , methodology and AI based power optimization solutions. You will… more
- Google (Mountain View, CA)
- …be part of Google's Consumer Hardware Silicon team, developing high performance and low power hardware to enable Google's continuous innovations in this space. ... digital Intellectual Property (IP) and subsystems. + Experience in Design Verification (DV) Testbenches/Environments. Preferred qualifications: + Master's degree or… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design .* Debugging of Low power and multiple power ... , Industry's first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.* Work closely...and Digital Physical implementation.* Strong background in Digital logic Design , CMOS logic Design , Power … more
- Meta (Sunnyvale, CA)
- …Engineer, Physical Design Responsibilities: 1. Develop and own physical design implementation of multi-hierarchy low - power and high-performance designs, ... experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build... of an end-to-end IP or integration of ASIC/SoC design and point out lower power and… more
- Qualcomm (Santa Clara, CA)
- …and/or physical design to develop and verify critical high performance and low power CPU designs. * Anticipates, identifies, and solves highly complex ... project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows...problems to ensure design completeness, functionality, power , and performance. *… more
- Qualcomm (San Diego, CA)
- …Modelsim/Questa, VCFormal, Jaspergold, 0In and others. **Preferred Qualifications:** + Experience with Low power design verification, Formal verification and ... verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation… more
- Qualcomm (Santa Clara, CA)
- …paced Integrated Wireless Technology team you will be working on low power next generation Wifi subsystem related Physical design implementation. You will ... critical decisions for Block level Physical Implementation. Experience in low power physical design with...related issues is a must. Deep understanding of physical design flow and methodology is preferred. Minimum… more
- Qualcomm (Santa Clara, CA)
- …Analytical and problem-solving skills + Experience with C/C++, assembly language. + **Knowledge of low power design concepts and power management is ... will work closely with SoC Architects, software, validation and design teams to verify IP that meets power... verification for Qualcomm WIFI projects + Own end-end low power test bench architecture, test plan… more
- NVIDIA (Santa Clara, CA)
- …or deep learning accelerator design /architecture experience + Performance verification, low power or physical (synthesis/VLSI) design experience + ... Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and...+ Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power … more
- Google (Mountain View, CA)
- …qualifications: + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design Implementation including ... about benefits at Google (https://careers.google.com/benefits/) . + Define and implement innovative methodology schemes to improve Performance, Area and Power . +… more