• Mixed - Signal and ASIC

    Teradyne (Agoura Hills, CA)
    …Opportunity Overview Teradyne has an excellent opportunity for a talented Intern to join our Mixed Signal ASIC Test and Characterization team located in ... CA. + Setup and operation of lab instrumentation for test development of mixed signal ...Integrated Circuits "ASICs". + Assist with generation of the ASIC test plan by working with design,… more
    Teradyne (05/13/25)
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  • Analog/ Mixed Signal ASIC

    Qualcomm (San Diego, CA)
    …Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > Analog Mixed Signal Design **General Summary:** QCT Mixed - Signal ... 5G, AI/ML, compute, and automotive applications. MSIP design team consists of architects, analog/ mixed signal and digital designers, protocol and signal more
    Qualcomm (04/23/25)
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  • Mixed Signal SVE Engineer

    Qualcomm (San Diego, CA)
    …of ASIC design, verification, validation, integration, or related work experience. The ** Mixed Signal SVE team** is seeking talented engineers to support the ... Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience....silicon bring-up efforts for mixed signal IPs, such as **DDRPHY** and… more
    Qualcomm (03/04/25)
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  • Digital ASIC Design Engineer for High-Speed…

    Qualcomm (San Diego, CA)
    …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** Qualcomm mixed - signal IP design team is seeking talented senior ASIC ... - Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT, synthesis, FV,...compiler, Tessent, and Spyglass. **Preferred Qualifications** - Experience with mixed - signal IPs, such as SerDes, DDR, and… more
    Qualcomm (04/19/25)
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  • Sr. SOC/ ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …domain crossing paths at block and full chip level + Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
    SpaceX (04/15/25)
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  • SOC/ ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …design flow + Work with systems and architecture, SOC integration, verification, DFT, mixed signal , IP owners, synthesis, and place/route teams to address the ... SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
    SpaceX (04/15/25)
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  • Senior ASIC Design Verification Engineer

    NVIDIA (Santa Clara, CA)
    …verification methodologies is a huge plus. + Strong knowledge or work experience in Mixed signal and custom designed IPs solutions. + Good understanding of ... NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off...behavioral real number modeling and low level digital or mixed signal design concepts. + Strong knowledge… more
    NVIDIA (03/06/25)
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  • Senior HSIO Bench Test Engineer

    Qualcomm (San Diego, CA)
    …PLLs and leading edge LP-DDR & PC-DDR Subsystem components (DRAM, DRAM Controller, Mixed Signal PHY IP, IOs, Clocking architecture, Delay circuits, Power ... is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs ( System on...of VLSI technologies, CMOS analog and digital integrated circuits, mixed - signal and semiconductor physics. + Knowledge of… more
    Qualcomm (04/09/25)
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  • ATE Test Engineer, Silicon

    Google (Mountain View, CA)
    …secure manufacturing touch points. + Experience with development of secure digital and mixed signal test and automation methodologies and support internal ... and Product Engineering activities. you will work with ASIC Architecture, Design, Pre-silicon SOC Verification to implement secure...will work with various groups to develop digital and mixed signal test and automation… more
    Google (05/22/25)
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  • Lead Test Security Engineer, Silicon

    Google (San Diego, CA)
    …secure manufacturing touch points. + Experience with development of secure digital and mixed signal test and automation methodologies and support internal ... and Product Engineering activities. You will work with ASIC architecture, design, pre-silicon SOC verification to implement secure...will work with various groups to develop digital and mixed signal test and automation… more
    Google (05/08/25)
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  • Senior Characterization Engineer (Semiconductor…

    Teradyne (Agoura Hills, CA)
    …reports on the results/findings. The role will involve direct communication with Teradyne's ASIC design team, ATE test team and our internal customers. + ... We are the global test and automation specialists, powering next-generation technologies through...Signal /power integrity experience is preferred. + Experience with mixed signals (analog and digital). + Experience characterizing PLLs,… more
    Teradyne (04/15/25)
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  • Hardware Engineer, Senior

    Qualcomm (San Diego, CA)
    …+ Candidate needs to have excellent technical understanding and experience in RF/ mixed signal circuit design, SI, Power management concepts, ATE & Bench ... into volume production at SATs. + Excellent technical understanding and experience in RF/ mixed signal circuit design, SI, Power management concepts, ATE & Bench… more
    Qualcomm (03/04/25)
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  • Principal Memory Interface Systems Engineer

    Qualcomm (San Diego, CA)
    …communication technology. Engineers in the Interface Systems group work on mixed signal IP system architecture, interface standards, system-technology ... co-optimization, power and signal integrity, hardware/software co-design and post-Silicon bring-up to help...engineering, IP and SoC development teams to successfully develop, test and deploy the design to end-product. Working effectively… more
    Qualcomm (04/10/25)
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  • DFT Engineer - CPU

    Qualcomm (Santa Clara, CA)
    … engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then ... in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test , DFT, and debug + 6+ years of practical experience with test or… more
    Qualcomm (04/09/25)
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  • Functional Verification Applications Engineer…

    Siemens (Fremont, CA)
    …Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed - signal , and analog IC chip designs based on Siemens EDA's ... Testbench development using SV/UVM methodologies, Functional verification and modeling of digital/ mixed - signal ASICs and SoCs, Failure analysis and resolution,… more
    Siemens (05/17/25)
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  • Logic and Digital Circuit Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    …and intelligence. Make the choice to join us today. As a member of our Mixed - Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground ... algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and...SystemVerilog, logic design and circuit modeling in RTL for mixed - signal blocks; + Exposure to custom digital… more
    NVIDIA (05/10/25)
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  • Senior Digital Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. Make the choice to join us today. As a member of our Mixed - Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground ... Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed - signal blocks; Experience with industry standard verification methodologies, such as… more
    NVIDIA (04/30/25)
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  • Applications Engineer Consultant EDA Functional…

    Siemens (Fremont, CA)
    …Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed - signal , and analog IC chip designs based on Siemens EDA's ... Testbench development using SV/UVM methodologies, Functional verification and modeling of digital/ mixed - signal ASICs and SoCs, Failure analysis and resolution,… more
    Siemens (03/18/25)
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  • Sr. IC Layout Engineer (Starlink)

    SpaceX (Sunnyvale, CA)
    …working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in ... reliable internet to 5M+ users worldwide. We design, build, test , and operate all parts of the system -...layout at the technical level, and will work with RFIC/ mixed signal designers on full chip layout… more
    SpaceX (04/15/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …Digital Silicon Architects developing and implementing the next generation custom and semi-custom mixed signal ICs to drive our industry leading virtual and ... timing constraints, run synthesis and static timing analysis. 4. Support the test program development, chip validation and chip life until production maturity. 5.… more
    Meta (05/13/25)
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