- Google (Sunnyvale, CA)
- …of static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs ... field, or equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification,… more
- Qualcomm (San Diego, CA)
- …develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge ... with spice, version-to-version validation. + Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical… more
- Meta (Sunnyvale, CA)
- …PPA (Power, Performance, and area) of the design . **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical ... implementation of multi-hierarchy low-power ML Hardware design including physical -aware logic synthesis, floorplan, place and route, static timing analysis,… more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
- Qualcomm (San Diego, CA)
- … physical -aware timing and IR drop ECO solutions ⦁ Collaborate closely with physical design and timing teams to drive methodologies to optimize power and ... methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing...experience with Primetime or Tempus ⦁ In-depth knowledge of physical design , preferably but not limited to… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant ... silicon interposer design and advanced packaging technologies. + Experience crafting physical design automation flows. In this role, you'll work to shape… more
- Capgemini (San Francisco, CA)
- …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification (DV) Engineer_ **Location:** _CA-San Francisco_ ... **Job description:** Analog/Mixed-Signal Design Verification **Key responsibilities:** + Extract modeling specifications...Develop timing model for the circuit working with layout engineer . + This role will provide the ability to… more
- Cisco (San Jose, CA)
- …and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing ... of what's possible! Your Impact You are a diligent Design /SDC Engineer with strong analytical skills and... team who oversees fullchip SDCs and works with physical design and DFT teams to close… more
- Google (Sunnyvale, CA)
- …Spice simulations, clock verification, and signoff. Preferred qualifications: + Experience in ASIC physical design , physical design flows, and ... delivering unparalleled performance, efficiency, and integration. As a Circuits Design Engineer , Clock Design you...Design you will collaborate with the architecture, logic design DFT, physical design , and… more
- The Boeing Company (Huntington Beach, CA)
- … practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …in next engagements Job Requirements Minimum + 10+ years of industry Physical Design experience + BS degree Computer Science/Engineering, Electrical, ... the world of technology. We are excited to welcome highly talented hardware design leaders/managers and application engineer leaders/managers to join our Cadence… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... teams to define a unified interface + Work with Physical design engineers, floor planning, define timing...DFE, CTLE, CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools… more
- NVIDIA (Santa Clara, CA)
- …world class engineers to design and implement VLSI tools for RTL and physical design + Develop applications to enable project engineers with an emphasis on ... architectural, rtl, and gate level designs. As a software engineer , you will craft highly efficient software to automate... design knowledge. + Good understanding of VLSI physical design + Strong expertise in modern… more
- Broadcom (San Jose, CA)
- …knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough knowledge of high-speed Ethernet networking and ... and working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with… more
- Broadcom (San Jose, CA)
- …involve in engineering implementation spec writing from marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will ... team. You will work closely with marketing, architecture, firmware, physical and layout teams on full product development cycle...either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years… more
- Qualcomm (Santa Clara, CA)
- …crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements and ... Description: Principal Duties and Responsibilities** + Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... and developing flows at all phases of the digital design and functional verification. It is further expected that...well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate… more