- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... Sr. SOC / ASIC Timing Signoff & Front-End Implementation...+ Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
- SpaceX (Irvine, CA)
- SOC / ASIC Timing Signoff & Front-End Implementation...and understanding of their impact on physical design and timing closure + Familiar with ASIC ... the ultimate goal of enabling human life on Mars. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER...change order flows (Timing ECOs) and integrate them into physical design flow + Work with systems… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Physical Design Engineers...design of an end-to-end IP or integration of ASIC / SoC design and point out ... ) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities:...Knowledge of geometry/process/device technology implications on physical design . 16. Experience with large SOC designs… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Google (Sunnyvale, CA)
- …. + Work separately and collaboratively to create and review ASIC / SoC subsystem design architecture and microarchitecture specifications. ... Engineer, you will play an important role in designing ASIC / SoC hardware for Artificial Intelligence (AI) and...to evaluate features and their impact. + Work with physical design teams to ensure design… more
- SanDisk (Milpitas, CA)
- … development + Contribute to the development of best practices and methodologies for ASIC design within the organization + Optimize designs for power efficiency, ... architectures using advanced RTL techniques + Develop and optimize SoC subsystems, including CPU complex, DDR, Host, Flash, Debug,...design optimization + Proficiency in EDA tools for ASIC design and verification + Knowledge of… more
- Qualcomm (San Diego, CA)
- …low power designs. + Strong knowledge in the entire low power, high performance ASIC / SoC design flows (micro-architecture, RTL design , verification, ... PrimeTime PX (PTPX) and work with cross-functional teams - design , implementation, and physical design ...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing feedback. **Minimum ... teams and vendors. **Preferred Qualifications:** Preferred Qualifications: 16. Experience with SOC Design Integration & Front End Implementation 17. Experience… more
- Meta (Sunnyvale, CA)
- …Engineers in supporting them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing/congestion feedback. **Minimum ... teams and vendors. **Preferred Qualifications:** Preferred Qualifications: 20. Experience in SOC Design Integration and Front-End Implementation. 21. Knowledge… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... practical experience **Preferred Qualifications:** Preferred Qualifications: 17. Experience in SOC Design Integration and Front-End Implementation. 18. Knowledge… more
- Qualcomm (San Diego, CA)
- …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... **Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of...Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related… more
- SanDisk (Irvine, CA)
- …and reviewing **low-level firmware** in C/C++ and/or Python + Solid understanding of ** SoC design ** and processor architectures (eg, ARM, ARC) + Familiarity with ... for a **PCIe expert** with a strong background in ** ASIC and Firmware development** to help define, architect, and...products. In this high-impact role, you will drive the design of advanced SSD subsystems, write detailed specifications, and… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
- Amazon (Cupertino, CA)
- …Develop and execute design automation mechanisms and flows. * Work with physical design teams to achieve performance and area requirements. Mentorship & ... requirements including software applications, use models, system architecture and SoC architecture/micro-architecture solutions. * Participate in logic design … more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... solutions. Your Impact You will be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design . Key… more
- Meta (Sunnyvale, CA)
- …for Power, Performance, and Area 18. 2. Floor Planning and Placement 19. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 20. 4 ... to Job" online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/ physical ...domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence...with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out… more
- Google (Sunnyvale, CA)
- …or Computer Science, with an emphasis on computer architecture. + 5 years of experience in ASIC design with 3 years of experience working on security design . ... experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer, you will join a...to verify and debug RTL designs. + Work with physical design teams to ensure design… more