- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be working on ... with timing ECO creation and final timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency… more
- Qualcomm (Santa Clara, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting… more
- SpaceX (Irvine, CA)
- …computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode ... deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $160,000.00 - $220,000.00/per year Your actual level and… more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA /Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was... STA /Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level… more
- Qualcomm (San Diego, CA)
- … engineer to drive development of advanced methodologies in die-level IR drop, STA , and power. The engineer should be proficient in static timing analysis ... IR drop analysis and optimization is also helpful. The engineer is expected to propose, develop, and validate new...and optimization methodologies for interaction of IR drop and STA ⦁ Develop physical-aware timing and IR drop ECO… more
- Qualcomm (Folsom, CA)
- …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology… more
- Qualcomm (San Diego, CA)
- …developing good-by-construction hierarchical solution, as well as enabling the latest STA features to reduce conservatism in Signoff. **This role's responsibilities ... initiatives for compute and turn-around time reduction. + Correlation of STA tools with spice, version-to-version validation. + Provide solutions to the… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. 8. Analyze the… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the… more
- Qualcomm (Santa Clara, CA)
- …proactively find solutions. This candidate will be working with Design, Synthesis and STA teams closely to provide physical design feedback and improve the overall ... in Floor Planning (FP), Placement, Clock Tree Synthesis (CTS), STA closure, and Physical verification closure for critical WiFi...is a must. - Debugging capability for PV and STA flows is preferred. - UPF knowledge is preferred.… more
- Cisco (San Jose, CA)
- …of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a ... the boundaries of what's possible! Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- Meta (Sunnyvale, CA)
- …for large complex disaggregated ASICs, with exposure to library characterization, STA , modeling, extraction, variation analysis, aging, and signoff flows to build ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC vendor partners and Foundries… more
- Amazon (Sunnyvale, CA)
- …design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to make sure the top ... equivalent experience. * 7+ years of experience in ASIC implementation, ie, synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or… more
- Broadcom (Irvine, CA)
- …and 8+ years of industry experience in flow development , synthesis constraints development / STA is a must, or MSEE and 6+ years of industry experience. A strong ... be responsible for working on automating design flows, supporting synthesis deliverables & STA . Apart from this, the candidate is also expected to handle minimal… more
- Qualcomm (San Diego, CA)
- …multi-mode, multi-voltage domain designs using industry standard timing tools + STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain ... designs. + Work on automation scripts within STA /PD/synthesis tools for methodology development and flow optimization. + Pushing PPA to best possible extent using… more