- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
- The Boeing Company (Huntington Beach, CA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as… more
- Palo Alto Networks (Santa Clara, CA)
- …meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize ... military experience required + Minimum 8 years experience in ASIC design + Demonstrated success in taking...+ Debugging simulation, emulation, and silicon validation + Analyzing physical design reports and fixing timing and… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
- Cisco (San Jose, CA)
- …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- Qualcomm (San Diego, CA)
- …Engineering **General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the ... - Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT,... specification documents and verification plans - Work with physical design (PD) team for physical… more
- SpaceX (Irvine, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +...design and timing closure + Deep understanding of ASIC design flow, top-down and bottom-up … more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... solutions. Your Impact You will be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design . Key… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd: + Familiarity… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
- Palo Alto Networks (Santa Clara, CA)
- …to validate critical interfaces. Within the Hardware team, you collaborate closely with Board Design , ASIC Design , PCB Layout, and Validation Test. You will ... Component Engineers. **Your Impact** + Collaborate with a cross-functional team including: ASIC , Board design , PCB layout, Operations supply base management,… more
- Silvus Technologies (Irvine, CA)
- …of your career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of...skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a… more
- NVIDIA (Santa Clara, CA)
- …you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and ... high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog… more
- NVIDIA (Santa Clara, CA)
- Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group ... to amplify human creativity and intelligence. What you'll be doing: + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general… more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... What you'll be doing: + Lead and implement IC physical layout for mixed-signal functions like high speed SerDes,...and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools.… more
- NVIDIA (Santa Clara, CA)
- … Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic ... high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog… more