- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- The Boeing Company (Huntington Beach, CA)
- …opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part of our Boeing Electronic Products ... team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks...production designs + Professional experience with hardware-based integration and test of ASIC /FPGA designs + Proven record… more
- RTX Corporation (El Segundo, CA)
- …of a rapidly evolving global market. This position is for a motivated Senior Electrical or Computer engineering candidate to be involved in the design, ... Technologies team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL,... / FPGA digital architecture and design using RTL, timing closure, verification, and system integration + Recommend new… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- SpaceX (Irvine, CA)
- …work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... imagination and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative… more
- SpaceX (Sunnyvale, CA)
- …path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. + Run and debug non- timing and SDF annotated gate-level ... Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- Amazon (San Diego, CA)
- …in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing customer ... and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block...and DPI-C . Ensure that the block meets DFT, timing and power targets by working closely with the… more
- Google (Fremont, CA)
- Senior Silicon Bringup and Test Lead, Raxium - Fremont _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision ... + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC /SoC) design, with a focus on both digital logic design and Design… more
- L3Harris (Yorba Linda, CA)
- …with deep mastery and substantive technical expertise in hardware, RF Electrical, and ASIC design, development, test , and manufacturing as well as advanced ... layout, and timing . . 15+ years of experience in leading senior hardware engineering teams and hands-on detailed RF hardware engineering to successfully complete… more
- Silvus Technologies (Irvine, CA)
- …processing blocks while working with systems engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware ... (MSEE). + Basic MATLAB skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a guarantee. It is based on… more
- Silvus Technologies (Los Angeles, CA)
- …processing blocks while working with systems engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware ... Experience using MATLAB. + Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. +… more
- SpaceX (Sunnyvale, CA)
- …is providing fast, reliable internet to millions of users worldwide. We design, build, test , and operate all parts of the system - thousands of satellites, consumer ... cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
- Silvus Technologies (Irvine, CA)
- …including fixed point design of signal processing blocks. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware ... Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs. + Experience… more
- Silvus Technologies (Irvine, CA)
- …including fixed point design of signal processing blocks. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware ... a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and work closely with the FPGA Engineering team. The… more
- L3Harris (Anaheim, CA)
- …providing critical technology advancements in the areas of GPS/Position Navigation and Timing , and Range and Test Solutions. We offer competitive benefits, ... sensors, GPS navigation systems, aerospace status indicators, and range and test solutions. The L3Harris Interstate Electronics Corporation business was founded in… more