- NVIDIA (Santa Clara, CA)
- …NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the ... + In addition, you will help develop and deploy DFT methodologies for our next generation products. + You...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the next generation SoCs. ... for the implementation & verification including Scan, PMBIST, JTAG and other DFT 's related logic. Additionally, they will define and develop methodology for … more
- NVIDIA (Santa Clara, CA)
- …We need a creative individual who understand ASIC and SoC test methodology, DFT techniques, NPI and ATE test program development and release. The individual will ... time, speed up the NPI bringup process. the individual will work with our DFT team, test engineering team and product developing engineering team to bringup our… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions +...to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- Google (San Diego, CA)
- …relates to design and testing Data analysis. + Experience with Design for test ( DFT ) techniques and structural tests such as Scan/ATPG, JTAG and memory Built-in self ... SoC (AI centric) Product Specifications and Design for testing ( DFT ) Architecture reviews and generate New Product Introduction (NPI)… more
- Google (Mountain View, CA)
- …Testing, (SLT) using Advantest SLT platform. + Experience with design for test ( DFT ) techniques and structural tests such as Scan/ATPG, JTAG and memory BIST and ... Google (https://careers.google.com/benefits/) . + Perform SoC product specifications and DFT architecture reviews and generate NPI characterization, test, and… more
- Qualcomm (San Diego, CA)
- …Digital Test Engineering (Mixed Signal, Microprocessors, HSIO, Logic, Memory, DFT , DFM, Machine Learning, SW Development), adjacent disciplines (Yield Management, ... development using Java/C++ for Test code development. . Understands Design for test ( DFT ) techniques and structural tests such as Scan/ATPG, JTAG and memory BIST is… more
- Capgemini (San Francisco, CA)
- **Job Title: RTL Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design/RTL Design engineer for our Full Time ... crafting timing constraint file, and work closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals +… more
- Capgemini (San Jose, CA)
- **About the job you're considering** Post-Silicon Validation Engineer + BSEE, MSEE (or higher) preferred, in Electrical Engineering. + Strong background in ... test program release! + Proven understanding of the latest DFT and test solutions. + Ability to thrive in...their journey towards Intelligent Industry. Capgemini Engineering has 65,000 engineer and scientist team members in over 30 countries… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... need to see: + BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD) a plus. + 5+ years… more
- Amazon (San Diego, CA)
- …un-served and under-served communities around the world. Come work at Amazon! As Senior Silicon Reliability Engineer , you will engage with an experienced ... PCB design and fabrication processes. - Silicon debug, Design for Test ( DfT ), qualification, and release to production. - RF-HTOL hardware development: boards,… more
- NVIDIA (Santa Clara, CA)
- …deliver extraordinary solutions in a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to ... Excellent problem solving, collaborative, and interpersonal skills. + Knowledgeable in DFT architecture, BIST, fault models and fault detection methods, HTOL… more
- Amazon (San Diego, CA)
- …to unserved and underserved communities around the world. Come work at Amazon! As Senior RF ATE Engineer , you will engage with an experienced cross-disciplinary ... firmware on DUTs to reduce test time and increase self-testability. - Analog DfT and RF-BIST techniques. - Performing RF measurements such as load pull,… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... experience in implementing Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most forward-thinking and hardworking… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... synthesis and verification, knowledge of Place and Route, and understanding of Design-for-test ( DFT ) is a plus. + Proficiency in scripting language, such as, Perl,… more
- General Atomics (Poway, CA)
- …We have a unique and exciting opportunity for an experienced RF Sensor Systems engineer to work in the GA-ASI Agile Mission System (AMS) division on a family ... Manifold, Doppler, Pulse Doppler, Waveform, Interferometry, Phase Shift, CFAR, DFT , Multi-Static, DSP, Digital Signal Processing **Salary:** $128,130 - $229,358… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... + Understanding of high-speed clock distribution and planning as well as impact of DFT logic in timing convergence. + Knowledge of circuits and SPICE, as well as… more
- NVIDIA (Santa Clara, CA)
- …and Iread + Product Guidance: Collaborate with architecture, RTL, place & route, DFT , CAD, circuit design, yield operations, and even external foundries to provide ... our exclusive engineering teams are rapidly growing. If you are a creative and autonomous engineer with a real passion for technology, we want to hear from you. Make… more
- NVIDIA (Santa Clara, CA)
- …circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design-for-test ( DFT ) and logic design is a plus. + Proficiency in scripting language, ... such as, Perl, Tcl, Make and automation methods/algorithms a certain plus. + Prior leadership experience a certain plus. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable… more