- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Google (Mountain View, CA)
- …or a related field, or equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools (eg, Genus, ... + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design Implementation including UPF/CPF,… more
- Qualcomm (San Diego, CA)
- …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...**Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of… more
- Google (Sunnyvale, CA)
- …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team working ... on SoC -level RTL design for our data center accelerators. You will ...to verify and debug RTL designs. + Work with physical design teams to ensure design… more
- SpaceX (Irvine, CA)
- …weekends to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/Timing Engineer /Level I: $120,000.00 - $145,000.00/per ... SOC /ASIC Timing Signoff & Front-End Implementation Engineer ...year Physical Design STA/Timing Engineer /Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
- Datavant (Sacramento, CA)
- …We're Looking For** Become a vital defender of our digital landscape as a SOC /SIRT engineer . You'll monitor and analyze security alerts, swiftly respond to ... effective coordination and communication across technical teams and stakeholders. + Design , mature, and implement advanced playbooks for triage, investigation, and… more
- Meta (Sunnyvale, CA)
- …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... Knowledge of geometry/process/device technology implications on physical design . 16. Experience with large SOC designs...physical design . 16. Experience with large SOC designs (>20M gates) with frequencies over 1GHZ. 17.… more
- Qualcomm (Santa Clara, CA)
- … engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using ... technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU,… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks +… more
- Umbra Lab (Santa Barbara, CA)
- …that has never meaningfully existed before. We are seeking a Senior FPGA Design Engineer (Space Systems), developing HDL based digital designs supporting ... identity, sexual orientation, race, color, religious creed, national origin, physical or mental disability, protected veteran status, or any...+ 7+ years of proven, relevant experience in digital design with FPGA and SoC devices. +… more
- The Boeing Company (El Segundo, CA)
- …& Weapons Systems has an exciting opportunity for a **Computer Architect/Embedded Computing Systems Design Engineer (Lead or Senior)** to join us as part of our ... design creativity and positive impact; applying expertise in FPGA/ SoC /processor-based design and development, high-speed memory systems, communication… more
- Qualcomm (San Diego, CA)
- …a CPU PPA Pathfinding Engineer , you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams to lead the cutting-edge ... + Strong data analytical skills to identify and address physical design issues. + Experience in pre-post...methods relevant to the designs. + Partner with Process, SoC and Post-silicon teams to analyze, improve design… more
- Meta (San Diego, CA)
- …Experience in SoC bus and interconnect protocols 12. Knowledge of physical design and low-power implementation 13. Experience with high-speed I/O protocols ... power machine learning accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital… more
- Google (Sunnyvale, CA)
- …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Engineer , you will play an important role in designing ... + Work separately and collaboratively to create and review ASIC/ SoC subsystem design architecture and microarchitecture specifications....to evaluate features and their impact. + Work with physical design teams to ensure design… more
- Cisco (San Jose, CA)
- …foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams. * Experience working with Package and ... for verification robustness. * Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend,… more
- Broadcom (San Jose, CA)
- …Hands-on expertise with Physical verification and place-and-route tools for ASIC/ SoC design is essential **Education/Experience:** + BS degree in Electrical ... please Sign-In before you apply.** **Job Description:** Broadcom is looking for a Design Implementation Engineer with demonstrated expertise in key areas such as… more
- Qualcomm (Santa Clara, CA)
- …domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements ... clock domain crossing and design constraints to achieve timing closure of complex SoC cores. + Review and integrate HM constraints into SoC and ensure… more
- Capgemini (San Francisco, CA)
- …Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design /RTL Design engineer for our Full Time Employment with ... Capgemini Engineering. **Key Responsibilities:** + Perform detailed block design from system requirements and evolving specifications. + Perform RTL coding, Lint… more
- Broadcom (San Jose, CA)
- …accurate and efficient timing analysis and closure. Expertise in place-and-route tools for ASIC/ SoC design is a must. The ideal candidate should have strong ... Sign-In before you apply.** **Job Description:** Broadcom is looking for a ** Design Implementation Engineer ** with demonstrated expertise across key areas such… more